HD6417032F20V Renesas Electronics America, HD6417032F20V Datasheet - Page 98

• Manufacturer Part Number: HD6417032F20V
• Description: SH1 ROMLESS LEAD FREE
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7030r

Specifications of HD6417032F20V

• Core Processor: SH-1
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 112-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Section 5 Interrupt Controller (INTC)
5.2
There are four types of interrupt sources: NMI, user break, IRQ, and on-chip supporting module
interrupts.
Interrupt rankings are expressed as priority levels (0–16), with 0 the lowest and 16 the highest. An
interrupt set to level 0 is masked.
5.2.1
NMI is the highest-priority interrupt (level 16) and is always accepted. Input at the NMI pin is
edge-sensed. Either the rising or falling edge can be selected by setting the NMI edge select bit
(NMIE) in the interrupt control register (ICR). NMI interrupt exception handling sets the interrupt
mask level bits (I3–I0) in the status register (SR) to level 15.
5.2.2
A user break interrupt occurs when a break condition is satisfied in the user break controller
(UBC). A user break interrupt has priority level 15. User break interrupt exception handling sets
the interrupt mask level bits (I3–I0) in the status register (SR) to level 15. For further details on the
user break interrupt, see section 6, User Break Controller (UBC).
5.2.3
IRQ interrupts are requested by input from pins IRQ0–IRQ7. IRQ sense select bits 0–7 (IRQ0S–
IRQ7S) in the interrupt control register (ICR) can select low-level sensing or falling-edge sensing
for each pin independently. Interrupt priority registers A and B (IPRA and IPRB) can select
priority levels from 0–15 for each pin. IRQ interrupt exception handling sets the interrupt mask
level bits (I3–I0) in the status register (SR) to the priority level value of the IRQ interrupt that was
accepted.
Rev. 7.00 Jan 31, 2006 page 70 of 658
REJ09B0272-0700
Interrupt Sources
NMI Interrupts
User Break Interrupt
IRQ Interrupts