HD6417032F20V Renesas Electronics America, HD6417032F20V Datasheet - Page 351

SH1 ROMLESS LEAD FREE

HD6417032F20V

Manufacturer Part Number
HD6417032F20V
Description
SH1 ROMLESS LEAD FREE
Manufacturer
Renesas Electronics America
Series
SuperH® SH7030r
Datasheet

Specifications of HD6417032F20V

Core Processor
SH-1
Core Size
32-Bit
Speed
20MHz
Connectivity
EBI/EMI, SCI
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
32
Program Memory Type
ROMless
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
112-QFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HD6417032F20V
Manufacturer:
TI
Quantity:
201
Part Number:
HD6417032F20V
Manufacturer:
RENESAS
Quantity:
20
Bits 7–0—Next Data Enable 15–8 (NDER15–NDER8): NDER15–NDER8 select
enabling/disabling for TPC output groups 3 and 2 (TP15–TP8) in bit units.
Bit 7–0:
NDER15–NDER8 Description
0
1
11.2.7
TPCR is an eight-bit read/write register that selects output trigger signals for TPC outputs. TPCR
is initialized to H'FF by a reset. It is not initialized in standby mode.
Bits 7 and 6—Group 3 Compare Match Select 1 and 0 (G3CMS1 and G3CMS0): G3CMS1
and G3CMS0 select the compare match that triggers TPC output group 3 (TP15–TP12).
Bit 7:
G3CMS1
0
1
Bit
Initial value
Read/Write
Bit
Initial value
Read/Write
TPC Output Control Register (TPCR)
Bit 6:
G3CMS0
0
1
0
1
Disables TPC outputs TP15–TP8 (transfer from NDR15–NDR8 to PB15–PB8
is disabled)
Enables TPC outputs TP15–TP8 (transfer from NDR15–NDR8 to PB15–PB8
is enabled)
G3CMS1 G3CMS0 G2CMS1 G2CMS0 G1CMS1 G1CMS0 G0CMS1 G0CMS0
NDER15 NDER14 NDER13 NDER12 NDER11 NDER10 NDER9 NDER8
R/W
R/W
7
0
7
1
TPC output group 3 (TP15–TP12) output is triggered by compare match
in ITU channel 0
TPC output group 3 (TP15–TP12) output is triggered by compare match
in ITU channel 1
TPC output group 3 (TP15–TP12) output is triggered by compare match
in ITU channel 2
TPC output group 3 (TP15–TP12) output is triggered by compare match
in ITU channel 3
Description
R/W
R/W
6
0
6
1
Section 11 Programmable Timing Pattern Controller (TPC)
R/W
R/W
5
0
5
1
R/W
R/W
4
0
4
1
Rev. 7.00 Jan 31, 2006 page 323 of 658
R/W
R/W
3
0
3
1
R/W
R/W
2
0
2
1
REJ09B0272-0700
R/W
R/W
1
0
1
1
(Initial value)
(Initial value)
R/W
R/W
0
0
0
1

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