HD6417032F20V Renesas Electronics America, HD6417032F20V Datasheet - Page 624

• Manufacturer Part Number: HD6417032F20V
• Description: SH1 ROMLESS LEAD FREE
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7030r

Specifications of HD6417032F20V

• Core Processor: SH-1
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 112-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Appendix A On-Chip Supporting Module Registers
Table A.28 CHCR0–CHCR3 Bit Functions
Bit
15,14 Destination address
13,12 Source address mode 0 0
11–8
Rev. 7.00 Jan 31, 2006 page 596 of 658
REJ09B0272-0700
Bit name
mode bits 1, 0 (DM1,
DM0)
bits 1, 0 (SM1, SM0)
Resource select bits
3–0 (RS3–RS0)
Value
0 0
0 1
1 0
1 1
0 1
1 0
1 1
0 0 0 0 DREQ (external request *
0 0 0 1 Reserved (cannot be set)
0 0 1 0 DREQ (external request *
0 0 1 1 DREQ (external request *
0 1 0 0 RXIO (transfer request by receive-data-full interrupt of
0 1 0 1 TXIO (transfer request by transmit-data-empty
0 1 1 0 RXI1 (transfer request by receive-data-full interrupt of
0 1 1 1 TXI1 (transfer request by transmit-data-empty
1 0 0 0 IMIA0 (input capture A/compare match A interrupt
1 0 0 1 IMIA1 (input capture A/compare match A interrupt
1 0 1 0 IMIA2 (input capture A/compare match A interrupt
Description
Destination address is fixed
Destination address incremented (+1 for byte transfer;
+2 for word transfer)
Destination address decremented (–1 for byte
transfer; –2 for word transfer)
Reserved (cannot be set)
Source address is fixed
Source address incremented (+1 for byte transfer;
+2 for word transfer)
Source address decremented (–1 for byte transfer;
–2 for word transfer)
Reserved (cannot be set)
(Dual address mode)
on-chip SCI0) *
interrupt of on-chip SCI0) *
on-chip SCI1) *
interrupt of on-chip SCI1) *
request of on-chip ITU0) *
request of on-chip ITU1) *
request of on-chip ITU2) *
4
4
1
1
1
4
4
4
)
) (Single address mode *
) (Single address mode *
4
4
(Initial value)
(Initial value)
(Initial value)
2
3
)
)