HD6417032F20V Renesas Electronics America, HD6417032F20V Datasheet - Page 148

• Manufacturer Part Number: HD6417032F20V
• Description: SH1 ROMLESS LEAD FREE
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7030r

Specifications of HD6417032F20V

• Core Processor: SH-1
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 112-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Section 8 Bus State Controller (BSC)
Bit 7—Refresh Control (RFSHE): RFSHE determines whether or not to perform DRAM refresh
operations. When this bit is cleared to 0, no DRAM refresh control is performed and the refresh
timer counter (RTCNT) can be used as an 8-bit interval timer. When set to 1, DRAM refresh
control is performed.
Bit 7: RFSHE
0
1
Bit 6—Refresh Mode (RMODE): When DRAM refresh control is selected (RFSHE = 1),
RMODE selects whether to perform CAS-before-RAS (CBR) refresh or self-refresh. When this bit
is cleared to 0, a CBR refresh is performed at the cycle set in the refresh timer control/status
register (RTCSR) and refresh time constant register (RTCOR). When set to 1, the DRAM
performs a self-refresh. When refresh control is not selected (RFSHE = 0), the RMODE bit setting
is not valid. When canceling self-refresh, set RMODE to 0 with RFSHE set to 1.
Bit 6: RMODE
0
1
Bits 5 and 4—CBR Refresh Wait State Insertion Bits 1 and 0 (RLW1, RLW0): These bits
select the number of wait states to be inserted (1–4) during CAS-before-RAS refreshing. When
CBR refresh is performed and the RW1 bit in WCR1 is set to 1, the number of wait states selected
by RLW1 and RLW0 is inserted regardless of the WAIT signal. When the RW1 bit is cleared to 0,
the RLW1 and RLW0 bit settings are ignored and no wait states are inserted.
Bit 5:
RLW1
0
1
Bits 3–0—Reserved: These bits are always read as 0. The write value should always be 0.
Rev. 7.00 Jan 31, 2006 page 120 of 658
REJ09B0272-0700
Bit 4:
RLW0
0
1
0
1
Description
Refresh control disabled. RTCNT can be used as an 8-bit interval timer
Refresh control enabled
Description
CAS-before-RAS refresh
Self-refresh
Description
1 state inserted
2 states inserted
3 states inserted
4 states inserted
(Initial value)
(Initial value)
(Initial value)