HD6417032F20V Renesas Electronics America, HD6417032F20V Datasheet - Page 121

• Manufacturer Part Number: HD6417032F20V
• Description: SH1 ROMLESS LEAD FREE
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7030r

Specifications of HD6417032F20V

• Core Processor: SH-1
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 112-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

6.4
CPU Instruction Fetch Bus Cycle:
CPU Data Access Bus Cycle:
DMA Cycle:
Register settings: BARH = H'0000, BARL = H'0404, BBR = H'0054
Conditions set: Address = H'00000404, bus cycle = CPU, instruction fetch, read (operand size
not included in conditions)
A user break interrupt will occur immediately before the instruction at address H'00000404. If
the instruction at address H'00000402 can accept an interrupt, the user break exception
handling will be executed after that instruction is executed. The instruction at H'00000404 will
not be executed. The value saved to the PC is H'00000404.
Register settings: BARH = H'0015, BARL = H'389C, BBR = H'0058
Conditions set: Address = H'0015389C, bus cycle = CPU, instruction fetch, write (operand size
not included in conditions)
No user break interrupt occurs, because no instruction fetch cycle is ever a write cycle.
Register settings: BARH = H'0003, BARL = H'0147, BBR = H'0054
Conditions set: Address = H'00030147, bus cycle = CPU, instruction fetch, read (operand size
not included in conditions)
No user break interrupt occurs, because instructions are always fetched from even addresses. If
the first fetched address after a branch is odd and a user break is set on this address, however,
user break exception handling will be carried out after address error exception handling.
Register settings: BARH = H'0012, BARL = H'3456, BBR = H'006A
Conditions set: Address = H'00123456, bus cycle = CPU, data access, write, word
A user break interrupt occurs when word data is written to address H'00123456.
Register settings: BARH = H'00A8, BARL = H'0391, BBR = H'0066
Conditions set: Address = H'00A80391, bus cycle = CPU, data access, read, word
No user break interrupt occurs, because word data access is always to an even address.
Register setting: BARH = H'0076, BARL = H'BCDC, BBR = H'00A7
Conditions set: Address = H'0076BCDC, bus cycle = DMA, data access, read, longword
A user break interrupt occurs when longword data is read from address H'0076BCDC.
Register setting: BARH = H'0023, BARL = H'45C8, BBR = H'0094
Conditions set: Address = H'002345C8, bus cycle = DMA, instruction fetch, read (operand
size not included)
No user break interrupt occurs, because a DMA cycle includes no instruction fetch.
Setting User Break Conditions
Rev. 7.00 Jan 31, 2006 page 93 of 658
Section 6 User Break Controller (UBC)
REJ09B0272-0700