HD6417032F20V Renesas Electronics America, HD6417032F20V Datasheet - Page 204

• Manufacturer Part Number: HD6417032F20V
• Description: SH1 ROMLESS LEAD FREE
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7030r

Specifications of HD6417032F20V

• Core Processor: SH-1
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 112-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Section 8 Bus State Controller (BSC)
The maximum number of states from BREQ input to bus release are used when B is a cycle
comprising the maximum number of states for which the bus is not released; the number of states
is the maximum number of states for which bus is not released + approx. 4.5 states.
The maximum number of states for which the bus is not released requires careful investigation.
1. Cycles in which bus is not released
Rev. 7.00 Jan 31, 2006 page 176 of 658
REJ09B0272-0700
a.
b. TAS instruction read cycle and write cycle
The bus is never released during one bus cycle. For example, in the case of a longword
read (or write) in 8-bit ordinary space, one bus cycle consists of 4 memory accesses to 8-bit
ordinary space, as shown in figure 8.44. The bus is not released between these accesses.
Assuming one memory access to require 2 states, the bus is not released for a period of 8
states.
The bus is never released during a TAS instruction read cycle and write cycle (figure 8.45).
The TAS instruction read cycle and write cycle should be regarded as one bus cycle during
which the bus is not released.
One bus cycle
Figure 8.43 When BREQ
Figure 8.45 TAS Instruction Read Cycle and Write Cycle
Bus cycle
BREQ
BACK
CK
t
BRQS
A
Figure 8.44 One Bus Cycle
8 bits 8 bits
Read cycle
Cycle during which bus is
not released (1 bus cycle)
Cycle during which
bus is not released
BREQ is Input without Satisfying t
BREQ
BREQ
B
8 bits 8 bits
Write cycle
t
BACD1
Bus release
BRQS