HD6417032F20V Renesas Electronics America, HD6417032F20V Datasheet - Page 22

• Manufacturer Part Number: HD6417032F20V
• Description: SH1 ROMLESS LEAD FREE
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7030r

Specifications of HD6417032F20V

• Core Processor: SH-1
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 112-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

12.2 Register Descriptions ........................................................................................................ 341
12.3 Operation .......................................................................................................................... 346
12.4 Usage Notes ...................................................................................................................... 350
Section 13 Serial Communication Interface (SCI)
13.1 Overview........................................................................................................................... 353
13.2 Register Descriptions ........................................................................................................ 356
13.3 Operation .......................................................................................................................... 376
Rev. 7.00 Jan 31, 2006 page xx of xxvi
12.1.3 Pin Configuration................................................................................................. 340
12.1.4 Register Configuration......................................................................................... 341
12.2.1 Timer Counter (TCNT)........................................................................................ 341
12.2.2 Timer Control/Status Register (TCSR)................................................................ 342
12.2.3 Reset Control/Status Register (RSTCSR) ............................................................ 343
12.2.4 Notes on Register Access..................................................................................... 344
12.3.1 Operation in Watchdog Timer Mode ................................................................... 346
12.3.2 Operation in Interval Timer Mode ....................................................................... 348
12.3.3 Operation in Standby Mode ................................................................................. 348
12.3.4 Timing of Overflow Flag (OVF) Setting ............................................................. 349
12.3.5 Timing of Watchdog Timer Overflow Flag (WOVF) Setting.............................. 349
12.4.1 TCNT Write and Increment Contention .............................................................. 350
12.4.2 Changing CKS2–CKS0 Bit Values...................................................................... 350
12.4.3 Changing Watchdog Timer/Interval Timer Modes.............................................. 350
12.4.4 System Reset With WDTOVF............................................................................. 351
12.4.5 Internal Reset With Watchdog Timer .................................................................. 351
13.1.1 Features................................................................................................................ 353
13.1.2 Block Diagram..................................................................................................... 354
13.1.3 Input/Output Pins ................................................................................................. 355
13.1.4 Register Configuration......................................................................................... 355
13.2.1 Receive Shift Register.......................................................................................... 356
13.2.2 Receive Data Register.......................................................................................... 356
13.2.3 Transmit Shift Register ........................................................................................ 357
13.2.4 Transmit Data Register ........................................................................................ 357
13.2.5 Serial Mode Register............................................................................................ 358
13.2.6 Serial Control Register......................................................................................... 360
13.2.7 Serial Status Register ........................................................................................... 363
13.2.8 Bit Rate Register (BRR) ...................................................................................... 367
13.3.1 Overview.............................................................................................................. 376
13.3.2 Operation in Asynchronous Mode ....................................................................... 378
13.3.3 Multiprocessor Communication........................................................................... 389
13.3.4 Synchronous Operation........................................................................................ 397
.................................................... 353