HD6417032F20V Renesas Electronics America, HD6417032F20V Datasheet - Page 229

SH1 ROMLESS LEAD FREE

HD6417032F20V

Manufacturer Part Number
HD6417032F20V
Description
SH1 ROMLESS LEAD FREE
Manufacturer
Renesas Electronics America
Series
SuperH® SH7030r
Datasheet

Specifications of HD6417032F20V

Core Processor
SH-1
Core Size
32-Bit
Speed
20MHz
Connectivity
EBI/EMI, SCI
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
32
Program Memory Type
ROMless
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
112-QFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-

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Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HD6417032F20V
Manufacturer:
TI
Quantity:
201
Part Number:
HD6417032F20V
Manufacturer:
RENESAS
Quantity:
20
9.3.4
The DMAC supports the transfers shown in table 9.5. It can operate in single address mode or dual
address mode, which are defined by how many bus cycles the DMAC takes to access the transfer
source and transfer destination. The actual transfer operation timing varies with the bus mode. The
DMAC has two bus modes: cycle-steal mode and burst mode.
Table 9.5
Source
External device with
DACK
External memory
Memory-mapped external
device
On-chip memory
On-chip supporting
module
Single: Single address mode
Dual: Dual address mode
Address Modes:
Single Address Mode
In single address mode, both the transfer source and destination are external; one (selectable) is
accessed by a DACK signal while the other is accessed by an address. In this mode, the
DMAC performs the DMA transfer in 1 bus cycle by simultaneously outputting a transfer
request acknowledge DACK signal to one external device to access it while outputting an
address to the other end of the transfer. Figure 9.6 shows an example of a transfer between an
external memory and an external device with DACK in which the external device outputs data
to the data bus while that data is written in external memory in the same bus cycle.
DMA Transfer Types
Supported DMA Transfers
External
Device with
DACK
Not available
Single
Single
Not available
Not available
External
Memory
Single
Dual
Dual
Dual
Dual
Section 9 Direct Memory Access Controller (DMAC)
Memory-
Mapped
External
Device
Single
Dual
Dual
Dual
Dual
Destination
Rev. 7.00 Jan 31, 2006 page 201 of 658
Not available
On-Chip
Memory
Dual
Dual
Dual
Dual
REJ09B0272-0700
On-Chip
Supporting
Module
Not available
Dual
Dual
Dual
Dual

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