HD6417032F20V Renesas Electronics America, HD6417032F20V Datasheet - Page 372

• Manufacturer Part Number: HD6417032F20V
• Description: SH1 ROMLESS LEAD FREE
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7030r

Specifications of HD6417032F20V

• Core Processor: SH-1
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 112-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Section 12 Watchdog Timer (WDT)
Note: * Only 0 can be written in bit 7, to clear the flag.
Bit 7—Watchdog Timer Overflow (WOVF): WOVF indicates that TCNT has overflowed (from
H'FF to H'00) in watchdog timer mode. It is not set in interval timer mode.
Bit 7: WOVF
0
1
Bit 6—Reset Enable (RSTE): RSTE selects whether to reset the chip internally if the TCNT
overflows in watchdog timer mode.
Bit 6: RSTE
0
1
Bit 5—Reset Select (RSTS): RSTS selects the type of internal reset generated if TCNT overflows
in watchdog timer mode.
Bit 5: RSTS
0
1
Bits 4–0—Reserved: These bits are always read as 1. The write value should always be 1.
12.2.4
The watchdog timer’s TCNT, TCSR, and RSTCSR registers differ from other registers in that they
are more difficult to write. The procedures for writing and reading these registers are given below.
Writing to TCNT and TCSR: These registers must be written by a word transfer instruction.
They cannot be written by byte transfer instructions. TCNT and TCSR both have the same write
Rev. 7.00 Jan 31, 2006 page 344 of 658
REJ09B0272-0700
Bit
Initial value
Read/Write
Notes on Register Access
Description
No TCNT overflow in watchdog timer mode
Cleared when software reads WOVF, then writes 0 in WOVF
Set by TCNT overflow in watchdog timer mode
Description
Not reset when TCNT overflows
LSI not reset internally, but TCNT and TCSR reset within WDT.
Reset when TCNT overflows
Description
Power-on reset
Manual reset
WOVF
R/(W)*
7
0
RSTE
R/W
6
0
RSTS
R/W
5
0
—
—
4
1
—
—
3
1
—
—
2
1
—
—
1
1
(Initial value)
(Initial value)
(Initial value)
—
—
0
1