HD6417032F20V Renesas Electronics America, HD6417032F20V Datasheet - Page 187

• Manufacturer Part Number: HD6417032F20V
• Description: SH1 ROMLESS LEAD FREE
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7030r

Specifications of HD6417032F20V

• Core Processor: SH-1
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 112-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

refresh is performed when they match. RTCNT is simultaneously cleared to H'00 and
incrementing begins again.
When the clock is selected with the CKS2–CKS0 bits, RTCNT immediately begins to increment
from its current value. This means that when the RTCOR cycle is set after the CKS2–CKS0 bits
are set, the RTCNT count may already be higher than the RTCOR cycle. When this occurs, the
RTCNT will overflow once (from H'FF to H'00) and incrementing will start again. Since the CBR
refresh will not be performed until the RTCNT again matches the RTCOR value, the initial refresh
interval will be rather long. It is thus advisable to set the RTCOR cycle prior to setting the CKS2–
CKS0 bits and start it incrementing. When CBR refresh control is being performed after use as an
8-bit interval timer, the RTCNT count value may be in excess of the refresh cycle. For this reason,
clear RTCNT by writing H'00 before starting refresh control to assure a correct refresh interval.
When the RW1 bit in WCR1 is set to 1 and the read cycle is set to long pitch, the number of wait
states selected by the RLW1 and RLW0 bits in RCR will be inserted into the CBR refresh cycle,
regardless of the status of the WAIT signal. Figure 8.29 shows RTCNT operation and figure 8.30
shows the timing of the CBR refresh. For details on timing, see sections 20.1.3 (3) and 20.2.3 (3),
Bus Timing.
RTCOR
RAS
CAS
value
Figure 8.30 Output Timing for CAS-Before-RAS Refresh Signal
H'00
CK
RTCNT
value
Figure 8.29 Refresh Timer Counter (RTCNT) Operation
Clock
selected with
CKS2–CKS0
with RTCOR
Compare
T
match
Rp
CBR
CBR: CAS-before-RAS refresh
with RTCOR
Compare
T
match
CBR
Rr
with RTCOR
Compare
T
Rev. 7.00 Jan 31, 2006 page 159 of 658
match
Rc
CBR
Section 8 Bus State Controller (BSC)
with RTCOR
Compare
match
CBR
REJ09B0272-0700
Time