HD6417032F20V Renesas Electronics America, HD6417032F20V Datasheet - Page 86
HD6417032F20V
Manufacturer Part Number
HD6417032F20V
Description
SH1 ROMLESS LEAD FREE
Manufacturer
Renesas Electronics America
Series
SuperH® SH7030r
Datasheet
1.HD6417034AFI20.pdf
(689 pages)
Specifications of HD6417032F20V
Core Processor
SH-1
Core Size
32-Bit
Speed
20MHz
Connectivity
EBI/EMI, SCI
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
32
Program Memory Type
ROMless
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
112-QFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
HD6417032F20V
Manufacturer:
TI
Quantity:
201
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Section 4 Exception Handling
4.3
4.3.1
Address errors occur during instruction fetches and data reading/writing as shown in table 4.5.
Table 4.5
Type
Instruction fetch
Data read/write
Note: * See section 8, Bus State Controller (BSC), for details on the on-chip supporting module
4.3.2
When an address error occurs, address error exception handling starts after both the bus cycle that
caused the address error and the instructions that were being executed at that time, have been
completed. The CPU then:
1. Pushes SR onto the stack.
2. Pushes the program counter onto the stack. The PC value saved is the start address of the
3.
Rev. 7.00 Jan 31, 2006 page 58 of 658
REJ09BX0272-0700
instruction following the last instruction to be executed.
Fetches the exception handling routine start address from the exception vector table for the
address error that occurred and starts program execution from that address. The branch that
occurs here is not a delayed branch.
space.
Address Errors
Address Error Sources
Address Error Exception Handling
Bus Cycle
Address Error Sources
Bus Master
CPU
CPU or DMAC
Operation
Instruction fetch from even address
Instruction fetch from odd address
Instruction fetch from outside on-chip
supporting module space
Instruction fetch from on-chip supporting
module space
Access to word data from even address
Access to word data from odd address
Access to longword data aligned on
longword boundary
Access to longword data not aligned on
longword boundary
Access to word or byte data in on-chip
supporting module space*
Access to longword data in 16-bit on-
chip supporting module space*
Access to longword data in 8-bit on-chip
supporting module space*
Address Error
None (normal)
Address error
None (normal)
Address error
None (normal)
Address error
None (normal)
Address error
None (normal)
None (normal)
Address error
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