HD6417032F20V Renesas Electronics America, HD6417032F20V Datasheet - Page 394

• Manufacturer Part Number: HD6417032F20V
• Description: SH1 ROMLESS LEAD FREE
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7030r

Specifications of HD6417032F20V

• Core Processor: SH-1
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 112-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Section 13 Serial Communication Interface (SCI)
Bit 3—Parity Error (PER): PER indicates that data reception (with parity) ended abnormally
due to a parity error in asynchronous mode.
Bit 3: PER
0
1
Bit 2—Transmit End (TEND): TEND indicates that when the last bit of a serial character was
transmitted, TDR did not contain new transmit data, so transmission has ended. TEND is a read-
only bit and cannot be written.
Bit 2: TEND
0
1
Rev. 7.00 Jan 31, 2006 page 366 of 658
REJ09B0272-0700
Description
Receiving is in progress or has ended normally
Clearing the RE bit to 0 in the serial control register does not affect the PER bit,
which retains its previous value.
PER is cleared to 0 when:
A receive parity error occurred. When a parity error occurs, the SCI transfers the
receive data into RDR but does not set RDRF. Serial receiving cannot continue
while PER is set to 1. In synchronous mode, serial transmitting is also disabled.
PER is set to 1 if the number of 1s in receive data, including the parity bit, does
not match the even or odd parity setting of the parity mode bit (O/E) in the serial
mode register (SMR).
Description
Transmission is in progress
TEND is cleared to 0 when:
End of transmission
TEND is set to 1 when:
The chip is reset or enters standby mode
Software reads PER after it has been set to 1, then writes 0 in PER
Software reads TDRE after it has been set to 1, then writes 0 in TDRE
The DMAC writes data in TDR
The chip is reset or enters standby mode
TE is cleared to 0 in the serial control register (SCR)
TDRE is 1 when the last bit of a one-byte serial character is transmitted
(Initial value)
(Initial value)