HD6417032F20V Renesas Electronics America, HD6417032F20V Datasheet - Page 90
HD6417032F20V
Manufacturer Part Number
HD6417032F20V
Description
SH1 ROMLESS LEAD FREE
Manufacturer
Renesas Electronics America
Series
SuperH® SH7030r
Datasheet
1.HD6417034AFI20.pdf
(689 pages)
Specifications of HD6417032F20V
Core Processor
SH-1
Core Size
32-Bit
Speed
20MHz
Connectivity
EBI/EMI, SCI
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
32
Program Memory Type
ROMless
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
112-QFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
HD6417032F20V
Manufacturer:
TI
Quantity:
201
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Section 4 Exception Handling
4.5.3
An instruction located immediately after a delayed branch instruction is called an “instruction
placed in a delay slot.” If an undefined instruction is located in a delay slot, illegal slot instruction
exception handling begins executing when the undefined code is decoded. Illegal slot instruction
exception handling also begins when the instruction located in the delay slot is an instruction that
rewrites the program counter. In this case, exception handling begins when the instruction that
rewrites the PC is decoded. The CPU performs illegal slot exception handling as follows:
1. Saves the status register onto the stack.
2. Pushes the program counter value onto the stack. The PC value saved is the branch destination
3.
4.5.4
If an undefined instruction located other than in a delay slot (immediately after a delayed branch
instruction) is decoded, general illegal instruction exception handling is executed. The CPU
follows the same procedure as for illegal slot exception handling, except that the program counter
(PC) value pushed on the stack in general illegal instruction exception handling is the start address
of the illegal instruction with the undefined code.
Rev. 7.00 Jan 31, 2006 page 62 of 658
REJ09BX0272-0700
address of the delayed branch instruction immediately before the instruction that contains the
undefined code or rewrites the PC.
Fetches the exception handling routine start address from the vector table corresponding to the
exception that occurred, branches to that address, and starts executing the program. The
branch is not a delayed branch.
Illegal Slot Instruction
General Illegal Instructions
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