HD6417032F20V Renesas Electronics America, HD6417032F20V Datasheet - Page 659

• Manufacturer Part Number: HD6417032F20V
• Description: SH1 ROMLESS LEAD FREE
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7030r

Specifications of HD6417032F20V

• Core Processor: SH-1
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 112-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Table A.60 PACR1 Bit Functions
Bit
15,14 PA15 mode bits 1,0
13,12 PA14 mode bits 1,0
11,10 PA13 mode bits 1,0
9,8
7,6
5,4
3,2
0
Bit Name
(PA15MD1, PA15MD0)
(PA14MD1, PA14MD0)
(PA13MD1, PA13MD0)
PA12 mode bits 1,0
(PA12MD1, PA12MD0)
PA11 mode bits 1,0
(PA11MD1, PA11MD0)
PA10 mode bits 1,0
(PA10MD1, PA10MD0)
PA9 mode bits 1,0
(PA9MD1, PA9MD0)
PA8 mode bit (PA8MD)
Value
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Description
General-purpose input/output (PA15)
Interrupt request input (IRQ3)
Reserved
DMA transfer request input (DREQ1)
General-purpose input/output (PA14)
Interrupt request input (IRQ2)
Reserved
DMA transfer request acknowledge output (DACK1)
General-purpose input/output (PA13)
Interrupt request input (IRQ1)
ITU timer clock input (TCLKB)
DMA transfer request input (DREQ0)
General-purpose input/output (PA12)
Interrupt request input (IRQ0)
ITU timer clock input (TCKLA)
DMA transfer request acknowledge output (DACK0)
General-purpose input/output (PA11)
High data bus parity input/output (DPH)
ITU input capture input/output compare output (TIOCB1)
Reserved
General-purpose input/output (PA10)
Low data bus parity input/output (DPL)
ITU input capture input/output compare output (TIOCA1)
Reserved
General-purpose input/output (PA9)
Address hold output (AH)
A/D conversion trigger input (ADTRG)
Interrupt request output (IRQOUT)
General-purpose input/output (PA8)
Bus request input (BREQ)
Appendix A On-Chip Supporting Module Registers
Rev. 7.00 Jan 31, 2006 page 631 of 658
REJ09B0272-0700
(Initial value)
(Initial value)
(Initial value)
(Initial value)
(Initial value)
(Initial value)
(Initial value)
(Initial value)