HD6417032F20V Renesas Electronics America, HD6417032F20V Datasheet - Page 242

• Manufacturer Part Number: HD6417032F20V
• Description: SH1 ROMLESS LEAD FREE
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7030r

Specifications of HD6417032F20V

• Core Processor: SH-1
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 112-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Section 9 Direct Memory Access Controller (DMAC)
Rev. 7.00 Jan 31, 2006 page 214 of 658
REJ09B0272-0700
DREQ pin sampling timing in burst mode
In burst mode, the sampling timing differs depending on whether DREQ is detected by edge or
level.
When DREQ input is being detected by edge, once the falling edge of the DREQ signal is
detected, the DMA transfer continues until the transfer end conditions are satisfied, regardless
of the status of the DREQ pin. No sampling happens during this time. After the transfer ends,
sampling occurs every state until the TE bit of CHCR is cleared.
When DREQ input is being detected by level, once the DREQ input is detected, subsequent
sampling is performed at the end of every CPU or DMAC bus cycle in single address mode. In
dual address mode, subsequent sampling is performed at the start of every DMAC read cycle.
In both single address mode and dual address mode, if no DREQ input is detected at this time,
subsequent sampling occurs at every state.
Figures 9.23 and 9.24 show the DREQ pin sampling timing in burst mode when DREQ input is
detected by low level.
Figure 9.22 DREQ
Bus cycle
Note: When DREQ is negated at the fourth state of the DMAC cycle, the next DMA
Detection and DACK Active-Low) (Dual Address Mode, Bus Cycle = Address/Data
DREQ
DACK
CK
transfer will be executed because the sampling is performed at the second state
of the DMAC cycle.
DREQ Sampling Timing in Cycle-Steal Mode (Output with DREQ
DREQ
DREQ
CPU
CPU
CPU
Multiplex I/O Bus Cycle)
T1
DMAC(R)
T2
T3
T4
DMAC
(W)
CPU
DMAC (W): DMAC write cycle
DMAC (R): DMAC read cycle
T1
DMAC (R)
T2
T3
T4
DMAC
(W)
DREQ Level
DREQ
DREQ
CPU