HD6417032F20V Renesas Electronics America, HD6417032F20V Datasheet - Page 427

SH1 ROMLESS LEAD FREE

HD6417032F20V

Manufacturer Part Number
HD6417032F20V
Description
SH1 ROMLESS LEAD FREE
Manufacturer
Renesas Electronics America
Series
SuperH® SH7030r
Datasheet

Specifications of HD6417032F20V

Core Processor
SH-1
Core Size
32-Bit
Speed
20MHz
Connectivity
EBI/EMI, SCI
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
32
Program Memory Type
ROMless
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
112-QFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-

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3. The SCI checks the TDRE bit when it outputs the MSB (bit 7). If TDRE is 0, the SCI loads
4.
Transmitting and Receiving Data: SCI Initialization (Synchronous Mode): Before transmitting
or receiving, software must clear the TE and RE bits to 0 in the serial control register (SCR), then
initialize the SCI as follows.
When changing the communication mode or format, always clear the TE and RE bits to 0 before
following the procedure given below. Clearing TE to 0 sets TDRE to 1 and initializes the transmit
shift register (TSR). Clearing RE to 0, however, does not initialize the RDRF, PER, FER, and
ORER flags and receive data register (RDR), which retain their previous contents.
Figure 13.16 shows a sample flowchart for initializing the SCI.
Serial clock
Serial data
If clock output is selected, the SCI outputs eight serial clock pulses. If an external clock source
is selected, the SCI outputs data in synchronization with the input clock. Data is output from
the TxD pin in order from the LSB (bit 0) to the MSB (bit 7).
data from TDR into TSR, transmits the MSB, then begins serial transmission of the next frame.
If TDRE is 1, the SCI sets the TEND bit in SSR to 1, transmits the MSB, then holds the
transmit data pin (TxD) in the MSB state. If the transmit-end interrupt enable bit (TEIE) in
SCR is set to 1, a transmit-end interrupt (TEI) is requested at this time.
After the end of serial transmission, the SCK pin is held in the high state.
TDRE
TEND
Transmit direction
request
TXI
Figure 13.15 Example of SCI Transmit Operation
Bit 0
LSB
clears TDRE to 0
data in TDR and
handler writes
TXI interrupt
Bit 1
1 frame
request
TXI
Section 13 Serial Communication Interface (SCI)
MSB
Bit 7
Rev. 7.00 Jan 31, 2006 page 399 of 658
Bit 0
Bit 1
REJ09B0272-0700
Bit 6
request
Bit 7
TEI

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