HD6417032F20V Renesas Electronics America, HD6417032F20V Datasheet - Page 49

• Manufacturer Part Number: HD6417032F20V
• Description: SH1 ROMLESS LEAD FREE
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7030r

Specifications of HD6417032F20V

• Core Processor: SH-1
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 112-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

2.2.3
Byte (8-bit) immediate data is located in the instruction code. Immediate data accessed by the
MOV, ADD, and CMP/EQ instructions is sign-extended and is handled in registers as longword
data. Immediate data accessed by the TST, AND, OR, and XOR instructions is zero-extended and
is handled as longword data. Consequently, AND instructions with immediate data always clear
the upper 24 bits of the destination register.
Word or longword immediate data is not located in the instruction code but rather is stored in a
memory table. The memory table is accessed by an immediate data transfer instruction (MOV)
using the PC relative addressing mode with displacement.
2.3
2.3.1
All instructions are RISC type. Their features are as follows:
16-Bit Fixed Length: Every instruction is 16 bits long, making program coding much more
efficient.
One Instruction/Cycle: Basic instructions can be executed in one cycle using a pipeline system.
One-cycle instructions are executed in 50 ns at 20 MHz.
Data Length: Longword is the standard data length for all operations. Memory can be accessed in
bytes, words, or longwords. Byte or word data accessed from memory is sign-extended and
handled as longword data. Immediate data is sign-extended for arithmetic operations or zero-
extended for logic operations (handled as longword data).
Table 2.2
SH7000 Series CPU
MOV.W
ADD
...........
.DATA.W
Note: The address of the immediate data is accessed by @(disp, PC).
R1,R0
@(disp,PC),R1
Instruction Features
Immediate Data Format
RISC-Type Instruction Set
Sign Extension of Word Data
H'1234
Description
Data is sign-extended to 32 bits, and
R1 becomes H'00001234. It is next
operated upon by an ADD
instruction.
Rev. 7.00 Jan 31, 2006 page 21 of 658
Conventional CPUs
ADD.W
REJ09B0272-0700
#H'1234,R0
Section 2 CPU