HD6417032F20V Renesas Electronics America, HD6417032F20V Datasheet - Page 145

SH1 ROMLESS LEAD FREE

HD6417032F20V

Manufacturer Part Number
HD6417032F20V
Description
SH1 ROMLESS LEAD FREE
Manufacturer
Renesas Electronics America
Series
SuperH® SH7030r
Datasheet

Specifications of HD6417032F20V

Core Processor
SH-1
Core Size
32-Bit
Speed
20MHz
Connectivity
EBI/EMI, SCI
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
32
Program Memory Type
ROMless
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
112-QFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HD6417032F20V
Manufacturer:
TI
Quantity:
201
Part Number:
HD6417032F20V
Manufacturer:
RENESAS
Quantity:
20
8.2.5
The DRAM area control register (DCR) is a 16-bit read/write register that selects the type of
DRAM control signal, the number of precharge cycles, the burst operation mode, and the use of
address multiplexing. DCR settings are valid only when the DRAME bit in BCR is set to 1. It is
initialized to H'0000 by a power-on reset, but is not initialized by a manual reset or in standby
mode.
Bit 15—Dual-CAS or Dual-WE Select Bit (CW2): When accessing a 16-bit bus width space,
CW2 selects the dual-CAS or the dual-WE method. When cleared to 0, the CASH, CASL, and
WRL signals are valid ; when set to 1, the CASL, WRH, and WRL signals are valid. When
accessing an 8-bit space, only CASL and WRL signals are valid, regardless of the CW2 setting.
Bit 15L: CW2
0
1
Bit 14—RAS Down (RASD): When DRAM access pauses, RASD determines whether to keep
RAS low while waiting for the next DRAM access (RAS down mode) or return it to high (RAS up
mode). When cleared to 0, the RAS signal returns to high; when set to 1, it stays low.
Bit 14: RASD
0
1
Bit
Initial value
Read/Write
Bit
Initial value
Read/Write
DRAM Area Control Register (DCR)
Description
Dual-CAS: CASH, CASL, and WRL signals are valid
Dual-WE: CASL, WRH, and WRL signals are valid
Description
RAS up mode: Return RAS signal to high and wait for the next DRAM access
RAS down mode: Keep RAS signal low and wait for the next DRAM access
CW2
R/W
15
0
7
0
RASD
R/W
14
0
6
0
TPC
R/W
13
0
5
0
R/W
BE
12
0
4
0
Rev. 7.00 Jan 31, 2006 page 117 of 658
Section 8 Bus State Controller (BSC)
CDTY
R/W
11
0
3
0
MXE
R/W
10
0
2
0
REJ09B0272-0700
MXC1
R/W
9
0
1
0
(Initial value)
(Initial value)
MXC0
R/W
8
0
0
0

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