HD6417032F20V Renesas Electronics America, HD6417032F20V Datasheet - Page 89

SH1 ROMLESS LEAD FREE

HD6417032F20V

Manufacturer Part Number
HD6417032F20V
Description
SH1 ROMLESS LEAD FREE
Manufacturer
Renesas Electronics America
Series
SuperH® SH7030r
Datasheet

Specifications of HD6417032F20V

Core Processor
SH-1
Core Size
32-Bit
Speed
20MHz
Connectivity
EBI/EMI, SCI
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
32
Program Memory Type
ROMless
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
112-QFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-

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Part Number
Manufacturer
Quantity
Price
Part Number:
HD6417032F20V
Manufacturer:
TI
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Part Number:
HD6417032F20V
Manufacturer:
RENESAS
Quantity:
20
4.5
4.5.1
Table 4.8 shows the three types of instruction that start exception handling (trap instructions,
illegal slot instructions, and general illegal instructions).
Table 4.8
Type
Trap instruction
Illegal slot
instruction
General illegal
instructions
4.5.2
Trap instruction exception handling is carried out when a trap instruction (TRAPA) is executed.
The CPU then:
1. Saves the status register by pushing register contents onto the stack.
2. Pushes the program counter value onto the stack. The PC value saved is the start address of the
3. Reads the exception handling routine start address from the vector table corresponding to the
next instruction after the TRAPA instruction.
vector number specified in the TRAPA instruction, branches to that address, and starts
program execution. The branch is not a delayed branch.
Instruction Exceptions
Types of Instruction Exceptions
Trap Instruction
Types of Instruction Exceptions
Source Instruction
TRAPA
Undefined code or instruction
that rewrites the PC located
immediately after a delayed
branch instruction (delay slot)
Undefined code in other than
delay slot
Comments
Delayed branch instructions are: JMP, JSR,
BRA, BSR, RTS, RTE. Instructions that
rewrite the PC are: JMP, JSR, BRA, BSR,
RTS, RTE, BT, BF, and TRAPA
Rev. 7.00 Jan 31, 2006 page 61 of 658
Section 4 Exception Handling
REJ09B0272-0700

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