Chameleon-PIC Nurve Networks, Chameleon-PIC Datasheet - Page 21

• Manufacturer Part Number: Chameleon-PIC
• Description: MCU, MPU & DSP Development Tools PIC24 & PROPELLER DEV SYSTEM (SBC)
• Manufacturer: Nurve Networks

Specifications of Chameleon-PIC

• Processor To Be Evaluated: PIC24
• Data Bus Width: 16 bit
• Interface Type: USB, VGA, PS/2, I2C, ISP, SPI
• Operating Supply Voltage: 3.3 V, 5 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Port B (PB15:PB0) - Port B is a 16-bit bi-directional I/O port. All ports on the PIC contain Schmitt Trigger inputs for
improved noise immunity. Pins can drive from 3.0V to 3.6V and those with open drain capabilities can drive up to 5V
output. In addition pins can sink up to 4mA of current. All of Port B pins can be remapped to the different chip peripherals
such as SPI, UART, ECAN bus, in addition to being used as general purpose I/O.
/MCLR – Reset input. A low level on this pin for longer than the minimum pulse length will generate a reset, even if the
clock is not running.
OSCI (RA2) - Input to the inverting Oscillator amplifier and input to the internal clock operating circuit. Shared with Port A
pin 2 (RA2).
OSCO (RA3) – Output from the inverting Oscillator amplifier. Shared with Port A (RA3)
VCC – Main power, 3V.
VCAP/VDDCore – CPU charge pump filter capacitor to sustain 2.5V to the CPU core.
VSS – System ground.
AVDD - AVDD is the supply voltage pin for the analog modules. It should be externally connected to VCC, even if the
analog peripherals are not used.
AVSS – Ground reference for analog modules
The PIC24HJ is a 16-bit RISC-like architecture chip with most instructions being a single program memory word (24-bits
in size) and only three instructions requiring two words. The memory model is a “Hardware Architecture” meaning that
the data and memory are located in separate memories that are not addressed as a contiguous space, but rather as
separate memories with different instructions to read/write to them. This allows faster execution since the same buses
aren’t used to access data and program space. Therefore, you will typically access SRAM as a continuous 8K of memory
and program/FLASH memory is in a completely different address space. Additionally, the PIC24HJ maps registers as well
as all its I/O ports in the SRAM memory space for ease of access. Figure 1.6 show these memories.
TIP
Harvard as opposed to Von Neumann architecture are the two primary computer
memory organizations used in modern processors. Harvard was created at Harvard
University, thus the moniker, and likewise Von Neumann was designed by
mathematician John Von Neumann Von Neumann differs from Harvard in that Von
Neumann uses a single memory for both data and program storage.
© 2009 NURVE NETWORKS LLC “Exploring the Chameleon PIC 16-Bit”
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