MCIMX53-START Freescale Semiconductor, MCIMX53-START Datasheet - Page 113

• Manufacturer Part Number: MCIMX53-START
• Description: KIT DEVELOPMENT I.MX53
• Manufacturer: Freescale Semiconductor
• Series: i.MX53r
• Type: MCUr

Specifications of MCIMX53-START

• Contents: Board
• Silicon Manufacturer: Freescale
• Core Architecture: ARM
• Core Sub-architecture: Cortex - A8
• Silicon Core Number: I.MX5
• Silicon Family Name: I.MX53
• Peak Reflow Compatible (260 C): Yes
• Rohs Compliant: Yes
• Leaded Process Compatible: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: i.MX53
• Lead Free Status / Rohs Status: Supplier Unconfirmed

The user must use level shifters for 5.0 V compatibility on the ATA interface. The i.MX53xD PATA
interface is 3.3 V compatible.
The use of bus buffers introduces delay on the bus and skew between signal lines. These factors make it
difficult to operate the bus at the highest speed (UDMA-5) when bus buffers are used. If fast UDMA mode
operation is needed, this may not be compatible with bus buffers.
Another area of attention is the slew rate limit imposed by the ATA specification on the ATA bus.
According to this limit, any signal driven on the bus should have a slew rate between 0.4 and 1.2 V/ns with
a 40 pF load. Not many vendors of bus buffers specify slew rate of the outgoing signals.
When bus buffers are used, the ata_data bus buffer is special. This is a bidirectional bus buffer, so a
direction control signal is needed. This direction control signal is ata_buffer_en. When its high, the bus
should drive from host to device. When its low, the bus should drive from device to host. Steering of the
signal is such that contention on the host and device tri-state busses is always avoided.
In the timing equations, some timing parameters are used. These parameters depend on the
implementation of the i.MX53xD PATA interface on silicon, the bus buffer used, the cable delay and
cable skew.
Freescale Semiconductor
1
SRISE and SFALL shall meet this requirement when measured at the sender’s connector from 10–90% of full signal
amplitude with all capacitive loads from 15
SI1
SI2
SI3
ID
ATA Interface Signals
Rising edge slew rate for any signal on ATA interface
Falling edge slew rate for any signal on ATA interface
Host interface signal capacitance at the host connector
Table 68
shows ATA timing parameters.
i.MX53xD Applications Processors for Consumer Products, Rev. 1
Table 67. AC Characteristics of All Interface Signals
Figure 65. PATA Interface Signals Timing Diagram
Parameter
–
40 pF where all signals have the same capacitive load value.
SI2
1
1
SI1
Symbol
C
S
S
host
rise
fall
Min
—
—
—
Electrical Characteristics
Max
1.25
1.25
20
Unit
V/ns
V/ns
pF
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