MCIMX53-START Freescale Semiconductor, MCIMX53-START Datasheet - Page 79

• Manufacturer Part Number: MCIMX53-START
• Description: KIT DEVELOPMENT I.MX53
• Manufacturer: Freescale Semiconductor
• Series: i.MX53r
• Type: MCUr

Specifications of MCIMX53-START

• Contents: Board
• Silicon Manufacturer: Freescale
• Core Architecture: ARM
• Core Sub-architecture: Cortex - A8
• Silicon Core Number: I.MX5
• Silicon Family Name: I.MX53
• Peak Reflow Compatible (260 C): Yes
• Rohs Compliant: Yes
• Leaded Process Compatible: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: i.MX53
• Lead Free Status / Rohs Status: Supplier Unconfirmed

1
2
3
4
4.7.7
This section describes the timing parameters of the I
module, and
Freescale Semiconductor
A device must internally provide a hold time of at least 300 ns for I2DAT signal in order to bridge the undefined region of the
falling edge of I2CLK.
The maximum hold time has only to be met if the device does not stretch the LOW period (ID no IC5) of the I2CLK signal.
A Fast-mode I2C-bus device can be used in a Standard-mode I2C-bus system, but the requirement of Set-up time (ID No IC7)
of 250 ns must be met. This automatically is the case if the device does not stretch the LOW period of the I2CLK signal.
If such a device does stretch the LOW period of the I2CLK signal, it must output the next data bit to the I2DAT line
max_rise_time (IC9) + data_setup_time (IC7) = 1000 + 250 = 1250 ns (according to the Standard-mode I2C-bus specification)
before the I2CLK line is released.
C
IC10
IC11
IC12
I2CLK
IC1
IC2
IC3
IC4
IC5
IC6
IC7
IC8
IC9
b
ID
I2DAT
= total capacitance of one bus line in pF.
I2CLK cycle time
Hold time (repeated) START condition
Set-up time for STOP condition
Data hold time
HIGH Period of I2CLK Clock
LOW Period of the I2CLK Clock
Set-up time for a repeated START condition
Data set-up time
Bus free time between a STOP and START condition
Rise time of both I2DAT and I2CLK signals
Fall time of both I2DAT and I2CLK signals
Capacitive load for each bus line (C
I
2
IC2
Table 53
C Module Timing Parameters
START
lists the I
i.MX53xD Applications Processors for Consumer Products, Rev. 1
IC10
IC6
IC8
Parameter
IC1
2
IC10
C module timing characteristics.
Table 53. I
IC5
IC4
b
Figure 41. I
)
2
C Module Timing Parameters
IC11
2
IC11
C Bus Timing
2
C module.
IC7
1.65 V–1.95 V, 2.7 V–3.3 V
START
Min
250
4.0
4.0
4.0
4.7
4.7
4.7
Supply Voltage =
10
0
—
—
—
Figure 41
Standard Mode
1
depicts the timing of I
3.45
1000
Max
300
400
—
—
—
—
—
—
—
—
2
IC3
STOP
Electrical Characteristics
20 + 0.1C
20 + 0.1C
Supply Voltage =
2.7 V–3.3 V
100
Fast Mode
Min
2.5
0.6
0.6
1.3
0.6
1.3
0.6
0
—
IC9
1
3
b
b
4
4
START
Max
0.9
300
300
400
—
—
—
—
—
—
—
—
2
C
2
Unit
µ
µ
µ
µ
µ
µ
µ
ns
µ
ns
ns
pF
s
s
s
s
s
s
s
s
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