MCIMX53-START Freescale Semiconductor, MCIMX53-START Datasheet - Page 167

• Manufacturer Part Number: MCIMX53-START
• Description: KIT DEVELOPMENT I.MX53
• Manufacturer: Freescale Semiconductor
• Series: i.MX53r
• Type: MCUr

Specifications of MCIMX53-START

• Contents: Board
• Silicon Manufacturer: Freescale
• Core Architecture: ARM
• Core Sub-architecture: Cortex - A8
• Silicon Core Number: I.MX5
• Silicon Family Name: I.MX53
• Peak Reflow Compatible (260 C): Yes
• Rohs Compliant: Yes
• Leaded Process Compatible: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: i.MX53
• Lead Free Status / Rohs Status: Supplier Unconfirmed

Freescale Semiconductor
KEY_ROW3
KEY_ROW4
LVDS_BG_RE
S
LVDS0_CLK_
N
LVDS0_CLK_
P
LVDS0_TX0_
N
LVDS0_TX0_P AA17
LVDS0_TX1_
N
LVDS0_TX1_P AC17
LVDS0_TX2_
N
LVDS0_TX2_P AA16
LVDS0_TX3_
N
LVDS0_TX3_P AC15
LVDS1_CLK_
N
LVDS1_CLK_
P
LVDS1_TX0_
N
LVDS1_TX0_P AB14
LVDS1_TX1_
N
LVDS1_TX1_P AB13
LVDS1_TX2_
N
LVDS1_TX2_P AB12
Package Pin
Name
D4
E6
AA14
AB16
AC16
Y17
AB17
Y16
AB15
AA13
Y13
AC14
AC13
AC12
Table 110. 19 x 19 mm Signal Assignments, Power Rails, and I/O (continued)
Package
Assign
ment
Pin
i.MX53xD Applications Processors for Consumer Products, Rev. 1
NVCC_KEYPAD
NVCC_KEYPAD
NVCC_LVDS_BG
NVCC_LVDS
NVCC_LVDS
NVCC_LVDS
NVCC_LVDS
NVCC_LVDS
NVCC_LVDS
NVCC_LVDS
NVCC_LVDS
NVCC_LVDS
NVCC_LVDS
NVCC_LVDS
NVCC_LVDS
NVCC_LVDS
NVCC_LVDS
NVCC_LVDS
NVCC_LVDS
NVCC_LVDS
NVCC_LVDS
Power Rail
ANALOG
UHVIO
UHVIO
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
I/O Buffer
Type
Mode
ALT1
ALT1
—
ALT0
ALT0
ALT0
ALT0
ALT0
ALT0
ALT0
ALT0
ALT0
ALT0
ALT0
ALT0
ALT0
ALT0
ALT0
ALT0
ALT0
ALT0
Alt.
GPIO-4 gpio4_GPIO[13]
GPIO-4 gpio4_GPIO[15]
LDB
GPIO-7 gpio7_GPI[25]
GPIO-7 gpio7_GPI[24]
GPIO-7 gpio7_GPI[31]
GPIO-7 gpio7_GPI[30]
GPIO-7 gpio7_GPI[29]
GPIO-7 gpio7_GPI[28]
GPIO-7 gpio7_GPI[27]
GPIO-7 gpio7_GPI[26]
GPIO-7 gpio7_GPI[23]
GPIO-7 gpio7_GPI[22]
GPIO-6 gpio6_GPI[27]
GPIO-6 gpio6_GPI[26]
GPIO-6 gpio6_GPI[31]
GPIO-6 gpio6_GPI[30]
GPIO-6 gpio6_GPI[29]
GPIO-6 gpio6_GPI[28]
GPIO-6 gpio6_GPI[25]
GPIO-6 gpio6_GPI[24]
Package Information and Contact Assignments
Out of Reset Condition
LVDS_BG_RES
Block I/O
Directio
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
—
n
1
100 KΩ PU
360 KΩ PD
Config./
Floating
Floating
Floating
Floating
Floating
Floating
Floating
Floating
Floating
Floating
Floating
Floating
Floating
Floating
Floating
Floating
Floating
Floating
Value
—
167