MCIMX53-START Freescale Semiconductor, MCIMX53-START Datasheet - Page 128

• Manufacturer Part Number: MCIMX53-START
• Description: KIT DEVELOPMENT I.MX53
• Manufacturer: Freescale Semiconductor
• Series: i.MX53r
• Type: MCUr

Specifications of MCIMX53-START

• Contents: Board
• Silicon Manufacturer: Freescale
• Core Architecture: ARM
• Core Sub-architecture: Cortex - A8
• Silicon Core Number: I.MX5
• Silicon Family Name: I.MX53
• Peak Reflow Compatible (260 C): Yes
• Rohs Compliant: Yes
• Leaded Process Compatible: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: i.MX53
• Lead Free Status / Rohs Status: Supplier Unconfirmed

Electrical Characteristics
4.7.16
This section describes the timing parameters of the SSI module. The connectivity of the serial
synchronous interfaces are summarized in
128
(Output)
STCLK
(Input)
SRCK
SSI Timing Parameters
•
•
AUDMUX port 1
AUDMUX port 2
AUDMUX port 3
AUDMUX port 4
AUDMUX port 5
AUDMUX port 6
AUDMUX port 7
The terms WL and BL used in the timing diagrams and tables refer to
Word Length (WL) and Bit Length (BL).
The SSI timing diagrams use generic signal names wherein the names
used in the i.MX53xD reference manual are channel specific signal
names. For example, a channel clock referenced in the IOMUXC
chapter as AUD3_TXC appears in the timing diagram as TXC.
Port
i.MX53xD Applications Processors for Consumer Products, Rev. 1
Signal Nomenclature
Table 79. AUDMUX Port Allocation
Figure 81. SPDIF Timing Diagram
AUD3
AUD4
AUD5
AUD6
SSI 1
SSI 2
SSI 3
Figure 82. STCLK Timing
stclkpl
srckpl
Table
V
V
M
M
79.
NOTE
Internal
Internal
External – AUD3 I/O
External – EIM or CSPI1 I/O through IOMUXC
External – EIM or SD1 I/O through IOMUXC
External – EIM or DISP2 through IOMUXC
Internal
stclkp
srckp
Type and Access
stclkph
srckph
V
V
M
M
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