MCIMX53-START Freescale Semiconductor, MCIMX53-START Datasheet - Page 14

• Manufacturer Part Number: MCIMX53-START
• Description: KIT DEVELOPMENT I.MX53
• Manufacturer: Freescale Semiconductor
• Series: i.MX53r
• Type: MCUr

Specifications of MCIMX53-START

• Contents: Board
• Silicon Manufacturer: Freescale
• Core Architecture: ARM
• Core Sub-architecture: Cortex - A8
• Silicon Core Number: I.MX5
• Silicon Family Name: I.MX53
• Peak Reflow Compatible (260 C): Yes
• Rohs Compliant: Yes
• Leaded Process Compatible: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: i.MX53
• Lead Free Status / Rohs Status: Supplier Unconfirmed

Modules List
14
Mnemonic
SECRAM
SPDIF
Block
SRTC
SPBA
SSI-1
SSI-2
SSI-3
SJC
Secure /
Non-secure RAM
Secure JTAG
Interface
Shared
Peripheral Bus
Arbiter
Sony Philips
Digital Interface
Secure Real
Time Clock
I2S/SSI/AC97
Interface
Block Name
i.MX53xD Applications Processors for Consumer Products, Rev. 1
Table 2. i.MX53xD Digital and Analog Blocks (continued)
Internal
Memory
System
Control
Peripherals
System
Control
Peripherals
Multimedia
Peripherals
Security
Connectivity
Peripherals
Subsystem
Secure / non-secure Internal RAM, controlled by SCC.
JTAG manipulation is a known hacker’s method of executing unauthorized
program code, getting control over secure applications, and running code in
privileged modes. The JTAG port provides a debug access to several
hardware blocks including the ARM processor and the system bus.
The JTAG port must be accessible during platform initial laboratory
bring-up, manufacturing tests and troubleshooting, as well as for software
debugging by authorized entities. However, in order to properly secure the
system, unauthorized JTAG usage should be strictly forbidden.
In order to prevent JTAG manipulation while allowing access for
manufacturing tests and software debugging, the i.MX53xD processor
incorporates a mechanism for regulating JTAG access. SJC provides four
different JTAG security modes that can be selected through an e-fuse
configuration.
SPBA (shared peripheral bus arbiter) is a two-to-one IP bus interface (IP
bus) arbiter.
A standard digital audio transmission protocol developed jointly by the Sony
and Philips corporations. Both transmitter and receiver functionalists are
supported.
The SRTC incorporates a special system state retention register (SSRR)
that stores system parameters during system shutdown modes. This
register and all SRTC counters are powered by dedicated supply rail
NVCC_SRTC_POW. The NVCC_SRTC_POW can be energized
separately even if all other supply rails are shut down. This register is helpful
for storing warm boot parameters. The SSRR also stores the system
security state. In case of a security violation, the SSRR mark the event
(security violation indication).
The SSI is a full-duplex synchronous interface used on the i.MX53xDA
processor to provide connectivity with off-chip audio peripherals. The SSI
interfaces connect internally to the AUDMUX for mapping to external ports.
The SSI supports a wide variety of protocols (SSI normal, SSI network, I2S,
and AC-97), bit depths (up to 24 bits per word), and clock/frame sync
options.
Each SSI has two pairs of 8 x 24 FIFOs and hardware support for an
external DMA controller in order to minimize its impact on system
performance. The second pair of FIFOs provides hardware interleaving of
a second audio stream, which reduces CPU overhead in use cases where
two time slots are being used simultaneously.
Brief Description
Freescale Semiconductor