MCIMX53-START Freescale Semiconductor, MCIMX53-START Datasheet - Page 114

• Manufacturer Part Number: MCIMX53-START
• Description: KIT DEVELOPMENT I.MX53
• Manufacturer: Freescale Semiconductor
• Series: i.MX53r
• Type: MCUr

Specifications of MCIMX53-START

• Contents: Board
• Silicon Manufacturer: Freescale
• Core Architecture: ARM
• Core Sub-architecture: Cortex - A8
• Silicon Core Number: I.MX5
• Silicon Family Name: I.MX53
• Peak Reflow Compatible (260 C): Yes
• Rohs Compliant: Yes
• Leaded Process Compatible: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: i.MX53
• Lead Free Status / Rohs Status: Supplier Unconfirmed

Electrical Characteristics
114
1
Values provided where applicable.
tcable1
tcable2
tskew1
tskew2
tskew3
tskew4
tskew5
tskew6
Name
ti_dh
ti_ds
tbuf
tsui
tco
tsu
thi
T
Set-up time ata_data to ata_iordy edge (UDMA-in only)
Propagation delay bus clock L-to-H to
Set-up time ata_data to bus clock L-to-H
Max difference in propagation delay bus clock L-to-H to any of following signals
Max difference in buffer propagation delay for any of following signals:
Max difference in buffer propagation delay for any of following signals ata_iordy,
Cable propagation delay for ata_data
Cable propagation delay for control signals ata_dior, ata_diow, ata_iordy,
Max difference in cable propagation delay between ata_iordy and ata_data (read)
Max difference in cable propagation delay between (ata_dior, ata_diow,
Max difference in cable propagation delay without accounting for ground bounce
Bus clock period (AHB_CLK_ROOT)
Hold time ata_iordy edge to ata_data (UDMA-in only)
ata_cs0, ata_cs1, ata_da2, ata_da1, ata_da0, ata_dior, ata_diow, ata_dmack,
ata_data, ata_buffer_en
Set-up time ata_iordy to bus clock H-to-L
Hold time ata_iordy to bus clock H to L
ata_cs0, ata_cs1, ata_da2, ata_da1, ata_da0, ata_dior, ata_diow, ata_dmack,
ata_data (write), ata_buffer_en
ata_cs0, ata_cs1, ata_da2, ata_da1, ata_da0, ata_dior, ata_diow, ata_dmack,
ata_data (write), ata_buffer_en
ata_data (read)
Max buffer propagation delay
ata_dmack
ata_dmack) and ata_cs0, ata_cs1, ata_da2, ata_da1, ata_da0, ata_data(write)
i.MX53xD Applications Processors for Consumer Products, Rev. 1
Table 68. PATA Timing Parameters
Description
UDMA0, UDMA1, UDMA2, UDMA3, UDMA4
UDMA2, UDMA3
UDMA0
UDMA1
UDMA4
UDMA5
UDMA5
Peripheral clock frequency
(7.5 ns for 133 MHz clock)
Contributing Factor
Freescale Semiconductor
Transceiver
Transceiver
Transceiver
12.0 ns
Value/
5.0 ns
4.6 ns
8.5 ns
8.5 ns
2.5 ns
Cable
Cable
Cable
Cable
Cable
15 ns
10 ns
7 ns
5 ns
4 ns
7 ns
1