MCIMX53-START Freescale Semiconductor, MCIMX53-START Datasheet - Page 39

• Manufacturer Part Number: MCIMX53-START
• Description: KIT DEVELOPMENT I.MX53
• Manufacturer: Freescale Semiconductor
• Series: i.MX53r
• Type: MCUr

Specifications of MCIMX53-START

• Contents: Board
• Silicon Manufacturer: Freescale
• Core Architecture: ARM
• Core Sub-architecture: Cortex - A8
• Silicon Core Number: I.MX5
• Silicon Family Name: I.MX53
• Peak Reflow Compatible (260 C): Yes
• Rohs Compliant: Yes
• Leaded Process Compatible: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: i.MX53
• Lead Free Status / Rohs Status: Supplier Unconfirmed

4.5.2
The DDR2/LVDDR2 interface mode fully complies with JESD79-2E DDR2 JEDEC standard release
April, 2008. The DDR3 interface mode fully complies with JESD79-3D DDR3 JEDEC standard release
April, 2008.
Table 21
Table 22
Freescale Semiconductor
1
2
3
4
AC input logic high
AC input logic low
AC differential input high voltage
AC differential input low voltage
Input AC differential cross point voltage
Over/undershoot peak
Over/undershoot area (above OVDD
or below OVSS)
AC input logic high
AC input logic low
AC differential input voltage
Input AC differential cross point voltage
Output AC differential cross point voltage
Single output slew rate
Skew between pad rise/fall asymmetry +
skew caused by SSN
Note that the JEDEC SSTL_18 specification (JESD8-15a) for class II operation supersedes any specification in this
document.
Vid(ac) specifies the input differential voltage |Vtr – Vcp| required for switching, where Vtr is the “true” input signal and Vcp is
the “complementary” input signal. The Minimum value is equal to Vih(ac) – Vil(ac).
The typical value of Vix(ac) is expected to be about 0.5 * OVDD. and Vix(ac) is expected to track variation of OVDD. Vix(ac)
indicates the voltage at which differential input signal must cross.
The typical value of Vox(ac) is expected to be about 0.5 * OVDD and Vox(ac) is expected to track variation in OVDD. Vox(ac)
indicates the voltage at which differential output signal must cross.
shows the AC parameters for LPDDR2 I/O operating in DDR2 mode.
shows the AC parameters for LPDDR2 I/O operating in LPDDR2 mode.
LPDDR2 I/O AC Electrical Characteristics
Parameter
Parameter
i.MX53xD Applications Processors for Consumer Products, Rev. 1
2
Table 22. LPDDR2 I/O LPDDR2 mode AC Characteristics
Table 21. LPDDR2 I/O DDR2 mode AC Characteristics
2
3
3
4
Vidh(ac)
Symbol
Vidl(ac)
Vih(ac)
Vix(ac)
Vil(ac)
Vpeak
Varea
Symbol Test Condition
Vih(ac)
Vox(ac)
Vil(ac)
Vid(ac)
Vix(ac)
t
SKD
tsr
Relative to OVDD/2
At 25 Ω to Vref
Test Condition
clk=266Mhz
clk=400Mhz
266MHz
—
—
—
—
—
—
—
—
—
—
Vref
Vref
Vref+0.25
Min
0.5
–
–
0.4
Vref + 0.22
—
—
0.175
0.125
-0.12
0.44
Min
—
—
—
0
Typ
—
—
—
—
—
—
—
1
1
Typ
—
—
—
—
—
—
—
Electrical Characteristics
Vref + 0.175
Vref + 0.125
Vref-0.25
OVDD
Max
Vref – 0.22
0.2
0.1
—
2
OVDD
Max
0.44
0.12
0.35
0.6
—
V/ns
Unit
ns
V
V
V
V
V
V*ns
Unit
V
V
V
V
V
V
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