MCIMX53-START Freescale Semiconductor, MCIMX53-START Datasheet - Page 54

• Manufacturer Part Number: MCIMX53-START
• Description: KIT DEVELOPMENT I.MX53
• Manufacturer: Freescale Semiconductor
• Series: i.MX53r
• Type: MCUr

Specifications of MCIMX53-START

• Contents: Board
• Silicon Manufacturer: Freescale
• Core Architecture: ARM
• Core Sub-architecture: Cortex - A8
• Silicon Core Number: I.MX5
• Silicon Family Name: I.MX53
• Peak Reflow Compatible (260 C): Yes
• Rohs Compliant: Yes
• Leaded Process Compatible: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: i.MX53
• Lead Free Status / Rohs Status: Supplier Unconfirmed

Electrical Characteristics
54
WE10 Clock rise to OE_B
WE11 Clock rise to OE_B
WE12 Clock rise to
WE13 Clock rise to
WE14 Clock rise to
WE15 Clock rise to
WE16 Clock rise to
WE17 Clock rise to
WE18 Input Data setup
WE19 Input Data hold
WE20 WAIT_B setup
WE21 WAIT_B hold time
WE3 BCLK High Level
WE4 Clock rise to
WE5 Clock rise to
WE6 Clock rise to
WE7 Clock rise to
WE8 Clock rise to
WE9 Clock rise to
ID
Width
address valid
address invalid
CSx_B valid
CSx_B invalid
WE_B Valid
WE_B Invalid
Valid
Invalid
BEy_B Valid
BEy_B Invalid
ADV_B Valid
ADV_B Invalid
Output Data Valid
Output Data
Invalid
time to Clock rise
time from Clock
rise
time to Clock rise
from Clock rise
Parameter
3
i.MX53xD Applications Processors for Consumer Products, Rev. 1
-0.5*t-1.25
-0.5*t-1.25
-0.5*t-1.25
-0.5*t-1.25
-0.5*t-1.25
-0.5*t-1.25
-0.5*t-1.25
0.5*t-1.25
0.5*t-1.25
0.5*t-1.25
0.5*t-1.25
0.5*t-1.25
0.5*t-1.25
0.5*t-1.25
Table 38. EIM Bus Timing Parameters (continued)
0.4*t
Min
2
2
2
2
BCD = 0
-0.5*t+1.75
-0.5*t+1.75
-0.5*t+1.75
-0.5*t+1.75
-0.5*t+1.75
-0.5*t+1.75
-0.5*t+1.75
0.5*t+1.75
0.5*t+1.75
0.5*t+1.75
0.5*t+1.75
0.5*t+1.75
0.5*t+1.75
0.5*t+1.75
Max
—
—
—
—
-t-1.25
-t-1.25
-t-1.25
-t-1.25
-t-1.25
-t-1.25
-t-1.25
t-1.25
t-1.25
t-1.25
t-1.25
t-1.25
t-1.25
t-1.25
0.8*t
Min
4
2
4
2
BCD = 1
-t+1.75
-t+1.75
-t+1.75
-t+1.75
-t+1.75
-t+1.75
-t+1.75
t+1.75
t+1.75
t+1.75
t+1.75
t+1.75
t+1.75
t+1.75
Max
—
—
—
—
-1.5*t-1.2
-1.5*t-1.2
-1.5*t-1.2
-1.5*t-1.2
-1.5*t-1.2
-1.5*t-1.2
-1.5*t-1.2
1.5*t-1.2
1.5*t-1.2
1.5*t-1.2
1.5*t-1.2
1.5*t-1.2
1.5*t-1.2
1.5*t-1.2
1.2*t
Min
—
—
—
—
5
5
5
5
5
5
5
5
5
5
5
5
5
5
BCD = 2
1.5*t +1.75 2*t-1.25
1.5*t +1.75 2*t-1.25
1.5*t +1.75 2*t-1.25
1.5*t +1.75 2*t-1.25
1.5*t +1.75 2*t-1.25
1.5*t +1.75 2*t-1.25
1.5*t +1.75 2*t-1.25
1
+1.75
+1.75
+1.75
+1.75
+1.75
+1.75
+1.75
-1.5*t
-1.5*t
-1.5*t
-1.5*t
-1.5*t
-1.5*t
-1.5*t
Max
—
—
—
—
Freescale Semiconductor
-2*t-1.25
-2*t-1.25
-2*t-1.25
-2*t-1.25
-2*t-1.25
-2*t-1.25
-2*t-1.25
1.6*t
Min
—
—
—
—
BCD = 3
-2*t+1.75
-2*t+1.75
-2*t+1.75
-2*t+1.75
-2*t+1.75
-2*t+1.75
-2*t+1.75
2*t+1.75
2*t+1.75
2*t+1.75
2*t+1.75
2*t+1.75
2*t+1.75
2*t+1.75
Max
—
—
—
—