MCIMX53-START Freescale Semiconductor, MCIMX53-START Datasheet - Page 85

KIT DEVELOPMENT I.MX53

MCIMX53-START

Manufacturer Part Number
MCIMX53-START
Description
KIT DEVELOPMENT I.MX53
Manufacturer
Freescale Semiconductor
Series
i.MX53r
Type
MCUr
Datasheets

Specifications of MCIMX53-START

Contents
Board
Silicon Manufacturer
Freescale
Core Architecture
ARM
Core Sub-architecture
Cortex - A8
Silicon Core Number
I.MX5
Silicon Family Name
I.MX53
Peak Reflow Compatible (260 C)
Yes
Rohs Compliant
Yes
Leaded Process Compatible
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With/related Products
i.MX53
Lead Free Status / Rohs Status
Supplier Unconfirmed

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Freescale Semiconductor
DIx_DISP_CLK
DISPx_DAT22
DISPx_DAT23
DIx_D0_CS
DIx_D1_CS
This mode works in compliance with recommendation ITU-R BT.656. The timing reference signals (frame start, frame end, line
start, and line end) are embedded in the 8-bit data bus. Only video data is supported, transmission of non-video related data
during blanking intervals is not supported.
Port Name
DIx_PIN11
DIx_PIN12
DIx_PIN13
DIx_PIN14
DIx_PIN15
DIx_PIN16
DIx_PIN17
Signal mapping (both data and control/synchronization) is flexible. The table provides examples.
i.MX53xD
DIx_PIN1
DIx_PIN2
DIx_PIN3
DIx_PIN4
DIx_PIN5
DIx_PIN6
DIx_PIN7
DIx_PIN8
(x=0, 1)
(General)
DAT[22]
DAT[23]
Signal
Name
RGB,
i.MX53xD Applications Processors for Consumer Products, Rev. 1
16-bit
RGB
Table 56. Video Signal Cross-Reference (continued)
RGB/TV Signal Allocation (Example)
18-bit
RGB
DRDY/DV
HSYNC
VSYNC
PixCLK
24 Bit
RGB
R[6]
R[7]
Q
LCD
YCrCb
8-bit
2
YCrCb
16-bit
YCrCb
20-bit
VSYNC_IN May be required for anti-tearing
Signal
Smart
Name
DRDY
CS0
CS1
RS1
RS2
WR
RD
VSYNC out
Additional frame/row synchronous
signals with programmable timing
Alternate mode of PWM output for
contrast or brightness control
Register select signal
Optional RS2
Data validation/blank, data enable
Additional data synchronous
signals with programmable
features/timing
Electrical Characteristics
Comment
1
85

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