MCIMX535DVV1C Freescale Semiconductor, MCIMX535DVV1C Datasheet - Page 12

• Manufacturer Part Number: MCIMX535DVV1C
• Description: IMX53 REV 2.1 COMM
• Manufacturer: Freescale Semiconductor

Specifications of MCIMX535DVV1C

• Rohs Compliant: YES
• Core Size: 32bit
• Program Memory Size: 288KB
• Cpu Speed: 1GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 529
• Supply Voltage Range: 1.25V To 1.35V
• Operating Temperature Range: -20°C To +85°C
• Msl: MSL 3 - 168 Hours
• Embedded Interface Type: I2C, SPI, UART
• Lead Free Status / Rohs Status: Supplier Unconfirmed

Modules List
12
BOOTROM
Mnemonic
IOMUXC
INTRAM
OWIRE
PWM-1
PWM-2
Block
PATA
KPP
LDB
IPU
IOMUX Control
Image
Processing Unit
Keypad Port
LVDS Display
Bridge
One-Wire
Interface
Parallel ATA
Pulse Width
Modulation
Internal RAM
Boot ROM
Block Name
i.MX53xD Applications Processors for Consumer Products, Rev. 3
Table 2. i.MX53xD Digital and Analog Blocks (continued)
System
Control
Peripherals
Multimedia
Peripherals
Connectivity
Peripherals
Connectivity
Peripherals
Connectivity
Peripherals
Connectivity
Peripherals
Connectivity
Peripherals
Internal
Memory
Internal
Memory
Subsystem
This module enables flexible I/O multiplexing. Each I/O pad has default as
well as several alternate functions. The alternate functions are software
configurable.
Version 3M IPU enables connectivity to displays, relevant processing and
synchronization. It supports two display ports and two camera ports,
through the following interfaces:
The processing includes:
The KPP supports an 8 × 8 external keypad matrix. The KPP features are
as follows:
LVDS display bridge is used to connect the IPU (image processing unit) to
external LVDS display interface. LDB supports two channels; each channel
has following signals:
On-chip differential drivers are provided for each pair.
One-wire support provided for interfacing with an on-board EEPROM, and
smart battery interfaces, for example, Dallas DS2502.
The PATA block is a AT attachment host interface. Its main use is to interface
with hard disk drives and optical disc drives. It interfaces with the ATA-6
compliant device over a number of ATA signals. It is possible to connect a
bus buffer between the host side and the device side.
The pulse-width modulator (PWM) has a 16-bit counter and is optimized to
generate sound from stored sample audio images. It can also generate
tones. The PWM uses 16-bit resolution and a 4 x 16 data FIFO to generate
sound.
Internal RAM, shared with VPU.
The on-chip memory controller (OCRAM) module, is an interface between
the system’s AXI bus, to the internal (on-chip) SRAM memory module. It is
used for controlling the 128 KB multimedia RAM, through a 64-bit AXI bus.
Supports secure and regular boot modes.
The ROM controller supports ROM patching.
• Legacy parallel interfaces
• Single/dual channel LVDS display interface
• Analog TV or VGA interfaces
• Image enhancement—color adjustment and gamut mapping, gamma
• Video/graphics combining
• Support for display backlight reduction
• Image conversion—resizing, rotation, inversion and color space
• Hardware de-interlacing support
• Synchronization and control capabilities, allowing autonomous
• Open drain design
• Glitch suppression circuit design
• Multiple keys detection
• Standby key press detection
• 1 clock pair
• 4 data pairs
correction and contrast enhancement
conversion
operation.
Brief Description
Freescale Semiconductor