MCIMX535DVV1C Freescale Semiconductor, MCIMX535DVV1C Datasheet - Page 99

• Manufacturer Part Number: MCIMX535DVV1C
• Description: IMX53 REV 2.1 COMM
• Manufacturer: Freescale Semiconductor

Specifications of MCIMX535DVV1C

• Rohs Compliant: YES
• Core Size: 32bit
• Program Memory Size: 288KB
• Cpu Speed: 1GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 529
• Supply Voltage Range: 1.25V To 1.35V
• Operating Temperature Range: -20°C To +85°C
• Msl: MSL 3 - 168 Hours
• Embedded Interface Type: I2C, SPI, UART
• Lead Free Status / Rohs Status: Supplier Unconfirmed

4.7.8.8
The following sections describes the types of asynchronous interfaces.
4.7.8.8.1
The IPU has four signal generator machines for asynchronous signal. Each machine generates IPU’s
internal control levels (0 or 1) by UP and DOWN that are defined in registers. Each asynchronous pin has
a dynamic connection with one of the signal generators. This connection is redefined again with a new
display access (pixel/component). The IPU can generate control signals according to system 80/68
requirements. The burst length is received as a result from predefined behavior of the internal signal
generator machines.
The access to a display is realized by the following:
Both system 80 and system 68k interfaces are supported for all described modes as depicted in
Figure
signals.
Each asynchronous access is defined by an access size parameter. This parameter can be different between
different kinds of accesses. This parameter defines a length of windows, when suitable controls of the
current access are valid. A pause between two different display accesses can be guaranteed by programing
suitable access sizes. There are no minimal/maximal hold/setup times hard defined by DI. Each control
signal can be switched at any time during access size.
Freescale Semiconductor
1
2
Chroma/Luma Delay Inequality
VIDEO PERFORMANCE IN HD MODE
Luma Frequency Response
Chroma Frequency Response
Luma Nonlinearity
Chroma Nonlinearity
Luma Signal-to-Noise Ratio
Chroma Signal-to-Noise Ratio
Guaranteed by design.
Guaranteed by characterization.
•
•
•
•
53,
CS (IPP_CS) chip select
WR (IPP_PIN_11) write strobe
RD (IPP_PIN_12) read strobe
RS (IPP_PIN_13) Register select (A0)
Figure
Asynchronous Interfaces
Standard Parallel Interfaces
Parameter
54, and
Table 63. TV Encoder Video Performance Specifications (continued)
i.MX53xD Applications Processors for Consumer Products, Rev. 3
Figure
55. The timing images correspond to active-low IPP_CS, WR and RD
2
0-30 MHz
0-15 MHz,
YCbCr 422 mode
0-30 MHz
0-15 MHz
Conditions
—
—
—
–0.2
–0.2
Min
—
—
—
—
—
Typ
1.0
3.2
3.4
62
72
—
—
Electrical Characteristics
Max
0.2
0.2
—
—
—
—
—
Figure
Unit
±ns
dB
dB
dB
dB
%
%
52,
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