MCIMX535DVV1C Freescale Semiconductor, MCIMX535DVV1C Datasheet - Page 117

• Manufacturer Part Number: MCIMX535DVV1C
• Description: IMX53 REV 2.1 COMM
• Manufacturer: Freescale Semiconductor

Specifications of MCIMX535DVV1C

• Rohs Compliant: YES
• Core Size: 32bit
• Program Memory Size: 288KB
• Cpu Speed: 1GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 529
• Supply Voltage Range: 1.25V To 1.35V
• Operating Temperature Range: -20°C To +85°C
• Msl: MSL 3 - 168 Hours
• Embedded Interface Type: I2C, SPI, UART
• Lead Free Status / Rohs Status: Supplier Unconfirmed

1
2
4.7.12.3 UDMA Output Timing
Figure 71
host terminates transfer,
Table 76
Freescale Semiconductor
There is a special timing requirement in the ATA host that requires the internal DIOW to go only high 3 clocks after the last
active edge on the DSTROBE signal. The equation given on this line tries to capture this constraint.
Make ton and toff big enough to avoid bus contention.
Parameter
tdzfs
ATA
tzah
tcyc
tcvh
tmli
trp
—
—
lists the timing parameters for UDMA out burst.
shows timing when the UDMA out transfer starts,
Parameter
Figure
Figure
Figure 70
from
tmli1
tdzfs
tzah
tx1
tcvh
toff
ton
tc1
trp
1
2
68,
69,
i.MX53xD Applications Processors for Consumer Products, Rev. 3
Figure 73
Table 75. UDMA in Burst Timing Parameters (continued)
Figure 71. UDMA Out Transfer Starts Timing Diagram
(tcyc – tskew) > T
trp (min) = time_rp
(time_rp
tmli1 (min) = (time_mlix + 0.4)
tzah (min) = (time_zah + 0.4)
tdzfs = (time_dzfs
tcvh = (time_cvh
ton = time_on
toff = time_off
shows timing when the UDMA out device terminates transfer, and
×
T) – (tco + tsu + 3T + 2
×
×
T – tskew1
T – tskew1
×
×
T) – (tskew1 + tskew2)
×
T) – (tskew1 + tskew2)
T – (tskew1 + tskew2 + tskew6)
Description
×
×
T
T
×
tbuf + 2
Figure 72
×
tcable2) > trfs (drive)
shows timing when the UDMA out
Electrical Characteristics
Controlling Variable
T big enough
time_dzfs
time_mlix
time_zah
time_cvh
time_rp
time_rp
—
117