MCIMX535DVV1C Freescale Semiconductor, MCIMX535DVV1C Datasheet - Page 48

• Manufacturer Part Number: MCIMX535DVV1C
• Description: IMX53 REV 2.1 COMM
• Manufacturer: Freescale Semiconductor

Specifications of MCIMX535DVV1C

• Rohs Compliant: YES
• Core Size: 32bit
• Program Memory Size: 288KB
• Cpu Speed: 1GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 529
• Supply Voltage Range: 1.25V To 1.35V
• Operating Temperature Range: -20°C To +85°C
• Msl: MSL 3 - 168 Hours
• Embedded Interface Type: I2C, SPI, UART
• Lead Free Status / Rohs Status: Supplier Unconfirmed

1
2
3
Electrical Characteristics
4.6.5
This section provides the relative timing requirements among various signals of NFC at the module level,
in each operational mode.
Timing parameters in
NFC mode (asymmetric mode) using two Flash clock cycles per one access of RE_B and WE_B.
Timing parameters in
NFC mode using one Flash clock cycle per one access of RE_B and WE_B.
With reference to the timing diagrams, a high is defined as 80% of signal value and low is defined as 20%
of signal value. All parameters are given in nanoseconds. The BGA contact load used in calculations is
20 pF (except for NF16 - 40 pF) and there is maximum drive strength on all contacts.
All timing parameters are a function of T, which is the period of the flash_clk clock (“enfc_clk” at system
level). This clock frequency can be controlled by the user, configuring CCM (SoC clock controller). The
clock is derived from emi_slow_clk after single divider.
Figure 35
48
4
5
Boot value NFC_FREQ_SEL Fuse High (burned)
Boot value NFC_FREQ_SEL Fuse Low
For RBB_MODE=1, using NANDF_RB0 signal for ready/busy indication. This mode require setting the delay line. See the
Reference Manual for details.
T
mode is 398 cycles of divided reference clock when DPLL starts after full reset.
Tdck is the time period of the output clock, dpdck_2.
emi_slow_clk (MHz)
dpdref
100 (Boot mode)
is the time period of the reference clock after predivider. According to the specification, the maximum lock time in FOL
demonstrates several examples of clock frequency settings.
133
NAND Flash Controller (NFC) Parameters
A potential limitation for minimum clock frequency may exist for some
devices. When the clock frequency is too low, the data bus capturing might
occur after the specified t
clock frequency above 25.6 MHz (that is, T = 39 ns) guaranties a proper
operation for devices having t
NFC_FREQ_SEL Fuse be set accordingly to initiate the boot with
33.33 MHz clock.
Figure
Figure
i.MX53xD Applications Processors for Consumer Products, Rev. 3
10,
10,
nfc_podf (Division Factor)
Figure
Figure
Table 35. NFC Clock Settings Examples
7
11,
11,
3
4
3
2
rhoh
1
2
Figure
Figure
(RE_B high to output hold) period. Setting the
rhoh
NOTE
> 15 ns. It is also recommended that the
12,
12,
Figure
Figure
13,
14,
enfc_clk (MHz)
Figure
Figure
44.33
14.29
33.33
33.33
66
3
3
15, and
15, and
Table 36
Table 36
Freescale Semiconductor
T-Clock Period (ns)
show symmetric
show the default
22.5
70
30
30
15