MCIMX535DVV1C Freescale Semiconductor, MCIMX535DVV1C Datasheet - Page 86

no-image

MCIMX535DVV1C

Manufacturer Part Number
MCIMX535DVV1C
Description
IMX53 REV 2.1 COMM
Manufacturer
Freescale Semiconductor
Datasheets

Specifications of MCIMX535DVV1C

Rohs Compliant
YES
Core Size
32bit
Program Memory Size
288KB
Cpu Speed
1GHz
Digital Ic Case Style
BGA
No. Of Pins
529
Supply Voltage Range
1.25V To 1.35V
Operating Temperature Range
-20°C To +85°C
Msl
MSL 3 - 168 Hours
Embedded Interface Type
I2C, SPI, UART
Lead Free Status / Rohs Status
Supplier Unconfirmed

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MCIMX535DVV1C
Manufacturer:
LRC
Quantity:
21 000
Part Number:
MCIMX535DVV1C
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Part Number:
MCIMX535DVV1C
Manufacturer:
FREESCALE
Quantity:
20 000
Part Number:
MCIMX535DVV1CR2
Manufacturer:
FREESCALE
Quantity:
556
Electrical Characteristics
SENSB_HSYNC goes to low at the end of line. Pixel clocks then become invalid and the CSI stops
receiving data from the stream. For next line the SENSB_HSYNC timing repeats. For next frame the
SENSB_VSYNC timing repeats.
4.7.8.2.3
The timing is the same as the gated-clock mode (described in
except for the SENSB_HSYNC signal, which is not used (see
valid and cause data to be latched into the input FIFO. The SENSB_PIX_CLK signal is inactive (states
low) until valid data is going to be transmitted over the bus.
The timing described in
different timing. The CSI can be programmed to support rising/falling-edge triggered SENSB_VSYNC;
active-high/low SENSB_HSYNC; and rising/falling-edge triggered SENSB_PIX_CLK.
4.7.8.3
Figure 46
the IPU.
86
SENSB_DATA,
SENSB_VSYNC,
SENSB_HSYNC
SENSB_PIX_CLK
(Sensor Output)
Table 59
SENSB_DATA[19:0]
depicts the sensor interface timing. SENSB_MCLK signal described here is not generated by
SENSB_PIX_CLK
SENSB_VSYNC
Electrical Characteristics
Non-Gated Clock Mode
lists the sensor interface timing characteristics.
Start of Frame
i.MX53xD Applications Processors for Consumer Products, Rev. 3
Figure 45
invalid
Figure 45. Non-Gated Clock Mode Timing Diagram
nth frame
Figure 46. Sensor Interface Timing Diagram
is that of a typical sensor. Some other sensors may have a slightly
1st byte
IP3
IP2
n+1th frame
Section 4.7.8.2.2, “Gated Clock
invalid
Figure
1/IP1
45). All incoming pixel clocks are
1st byte
Freescale Semiconductor
Mode,”)

Related parts for MCIMX535DVV1C