MCIMX535DVV1C Freescale Semiconductor, MCIMX535DVV1C Datasheet - Page 68

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MCIMX535DVV1C

Manufacturer Part Number
MCIMX535DVV1C
Description
IMX53 REV 2.1 COMM
Manufacturer
Freescale Semiconductor
Datasheets

Specifications of MCIMX535DVV1C

Rohs Compliant
YES
Core Size
32bit
Program Memory Size
288KB
Cpu Speed
1GHz
Digital Ic Case Style
BGA
No. Of Pins
529
Supply Voltage Range
1.25V To 1.35V
Operating Temperature Range
-20°C To +85°C
Msl
MSL 3 - 168 Hours
Embedded Interface Type
I2C, SPI, UART
Lead Free Status / Rohs Status
Supplier Unconfirmed

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Electrical Characteristics
1
4.7
The following subsections provide information on external peripheral interfaces.
4.7.1
The AUDMUX provides a programmable interconnect logic for voice, audio and data routing between
internal serial interfaces (SSIs) and external serial interfaces (audio and voice codecs). The AC timing of
AUDMUX external pins is governed by the SSI module. For more information, see the respective SSI
electrical specifications found within this document.
4.7.2
This section describes the timing parameters of the CSPI and ECSPI blocks. The CSPI and ECSPI have
separate timing parameters for master and slave modes. The nomenclature used with the CSPI / ECSPI
modules and the respective routing of these signals is shown in
68
DDR26(LP
To receive the reported setup and hold values, read calibration should be performed in order to locate the DQS in the middle
of DQ window.
DDR26
DDR27
DDR2)
ID
DQS (input)
DQ (input)
SDCLK_B
SDCLK
External Peripheral Interfaces Parameters
AUDMUX Timing Parameters
CSPI and ECSPI Timing Parameters
Minimum required DQ valid window width
except from LPDDR2
Minimum required DQ valid window width
for LPDDR2
DQS to DQ valid data
Figure 31. DDR SDRAM DQ vs. DQS and SDCLK Read Cycle
i.MX53xD Applications Processors for Consumer Products, Rev. 3
DDR27
Table 44. DDR SDRAM Read Cycle
Parameter
DATA
DDR26
DATA
DATA
DATA
Table
DATA
1
45.
Symbol
DATA
SDCLK = 400 MHz
0.425
0.275
Min
0.6
Freescale Semiconductor
DATA
0.475
Max
DATA
Unit
ns
ns
ns

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