MCIMX535DVV1C Freescale Semiconductor, MCIMX535DVV1C Datasheet - Page 85

• Manufacturer Part Number: MCIMX535DVV1C
• Description: IMX53 REV 2.1 COMM
• Manufacturer: Freescale Semiconductor

Specifications of MCIMX535DVV1C

• Rohs Compliant: YES
• Core Size: 32bit
• Program Memory Size: 288KB
• Cpu Speed: 1GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 529
• Supply Voltage Range: 1.25V To 1.35V
• Operating Temperature Range: -20°C To +85°C
• Msl: MSL 3 - 168 Hours
• Embedded Interface Type: I2C, SPI, UART
• Lead Free Status / Rohs Status: Supplier Unconfirmed

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4.7.8.2
There are three camera timing modes supported by the IPU.
4.7.8.2.1
Smart camera sensors, which include imaging processing, usually support video mode transfer. They use
an embedded timing syntax to replace the SENSB_VSYNC and SENSB_HSYNC signals. The timing
syntax is defined by the BT.656/BT.1120 standards.
This operation mode follows the recommendations of ITU BT.656/ ITU BT.1120 specifications. The only
control signal used is SENSB_PIX_CLK. Start-of-frame and active-line signals are embedded in the data
stream. An active line starts with a SAV code and ends with a EAV code. In some cases, digital blanking
is inserted in between EAV and SAV code. The CSI decodes and filters out the timing-coding from the data
stream, thus recovering SENSB_VSYNC and SENSB_HSYNC signals for internal use. On BT.656 one
component per cycle is received over the SENSB_DATA bus. On BT.1120 two components per cycle are
received over the SENSB_DATA bus.
4.7.8.2.2
The SENSB_VSYNC, SENSB_HSYNC, and SENSB_PIX_CLK signals are used in this mode. See
Figure
A frame starts with a rising edge on SENSB_VSYNC (all the timings correspond to straight polarity of the
corresponding signals). Then SENSB_HSYNC goes to high and hold for the entire line. Pixel clock is valid
as long as SENSB_HSYNC is high. Data is latched at the rising edge of the valid pixel clocks.
Freescale Semiconductor
The MSB bits are duplicated on LSB bits implementing color extension
The two MSB bits are duplicated on LSB bits implementing color extension
RGB 16 bits – supported in two ways: (1) As a “generic data” input – with no on-the-fly processing; (2) With on-the-fly
processing, but only under some restrictions on the control protocol.
YCbCr 16 bits - supported as a “generic-data” input – with no on-the-fly processing.
YCbCr 16 bits - supported as a sub-case of the YCbCr, 20 bits, under the same conditions (BT.1120 protocol).
YCbCr, 20 bits, supported only within the BT.1120 protocol (syncs embedded within the data stream).
44.
SENSB_DATA[19:0]
SENSB_PIX_CLK
SENSB_HSYNC
SENSB_VSYNC
Sensor Interface Timings
BT.656 and BT.1120 Video Mode
Gated Clock Mode
Start of Frame
i.MX53xD Applications Processors for Consumer Products, Rev. 3
invalid
nth frame
Figure 44. Gated Clock Mode Timing Diagram
1st byte
Active Line
n+1th frame
invalid
1st byte
Electrical Characteristics
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