MCIMX535DVV1C Freescale Semiconductor, MCIMX535DVV1C Datasheet - Page 52

• Manufacturer Part Number: MCIMX535DVV1C
• Description: IMX53 REV 2.1 COMM
• Manufacturer: Freescale Semiconductor

Specifications of MCIMX535DVV1C

• Rohs Compliant: YES
• Core Size: 32bit
• Program Memory Size: 288KB
• Cpu Speed: 1GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 529
• Supply Voltage Range: 1.25V To 1.35V
• Operating Temperature Range: -20°C To +85°C
• Msl: MSL 3 - 168 Hours
• Embedded Interface Type: I2C, SPI, UART
• Lead Free Status / Rohs Status: Supplier Unconfirmed

Electrical Characteristics
52
1
2
3
In case of NUM_OF_DEVICES is greater than 0 (for example, interleaved mode), then only during the data phase of
symmetric mode the setup time will equal 1.5T + 0.95.
t
Asymmetric mode:
Symmetric mode:
t
where t
EXTMC including I/O pad delay.
t
Tdl is composed of 4 delay-line units each generates an equal delay with min 1.25 ns and max 1 aclk period (T
is 1/4 aclk period for each delay-line unit, so all 4 delay lines together generates a total of 1 aclk period. T
“emi_slow_clk” of the system, which default value is 7.5 ns (133 MHz).
NF16
NF17
NF18
NF10
NF11
NF12
NF13
NF14
NF15
NF19
NF20
NF21
NF22
NF3
DSR
REpd
DSR
NF1
NF2
NF4
NF5
NF6
NF7
NF8
NF9
ID
is calculated by the following formula:
1
can be used to determine t
2
4
5
+ t
REpd
Dpd
NFRE_B High Hold Time
= 11.2 ns (including clock skew)
is RE propogation delay in the chip including I/O pad delay, and t
Ready to NFRE_B Low
NFWE_B Pulse Width
NFRE_B Pulse Width
Data Setup on READ
NFCE_B Setup Time
NFWE_B Hold Time
Data Hold on READ
Data Hold on READ
NFCE_B Hold Time
NFCLE setup Time
NFALE Setup Time
WE high to RE low
NFCLE Hold Time
NFALE Hold Time
READ Cycle Time
Write Cycle Time
Data Setup Time
CLE to RE delay
WE high to busy
Data Hold Time
CE to RE delay
Parameter
t
t
DSR =
DSR =
i.MX53xD Applications Processors for Consumer Products, Rev. 3
t
t
REpd
REpd
REA
+ t
+ t
Dpd +
max parameter with the following formula: t
Table 36. NFC—Timing Characteristics
Dpd
– Tdl
1
/
2
T – Tdl
Symbol
2
t
t
t
t
t
t
t
t
t
t
t
t
t
t
WHR
t
t
t
t
t
t
t
t
REH
DSR
DHR
DHR
CRE
CLS
CLH
ALH
CLR
ALS
WP
WC
WH
WB
CS
CH
DS
DH
RR
RP
RC
2
Asymmetric Mode Min
11.2 + 0.5T – Tdl
0.5T – 1.15
3T + 0.95
2T + 0.1
2T + 0.1
9T + 8.9
T – 4.45
2T–5.55
T – 4.45
T – 5.55
T – 1.15
T – 3.45
T – 1.4
T – 0.9
10.5T
1.5T
2T
2T
9T
—
—
0
Dpd
3
REA =
is Data propogation delay from I/O pad to
Symmetric Mode
1.5T – t
0.5T – 5.55
0.5T – 1.15
0.5T – 1.15
11.2 – Tdl
Tdl
0.5T – 1.4
0.5T – 0.9
1.5T–5.55
2T + 0.1
T – 4.45
3T+0.95
2T + 0.1
T – 4.45
9T + 8.9
T – 3.45
0.5T–1
T–0.5
10.5T
2
Min
9T
—
—
DSR
T
– 11.2
.
Freescale Semiconductor
2
aclk
is
2T
2T
aclk
T + 0.3
aclk
aclk
Max
6T
). Default
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
+ T
+ T