MCIMX535DVV1C Freescale Semiconductor, MCIMX535DVV1C Datasheet - Page 35

• Manufacturer Part Number: MCIMX535DVV1C
• Description: IMX53 REV 2.1 COMM
• Manufacturer: Freescale Semiconductor

Specifications of MCIMX535DVV1C

• Rohs Compliant: YES
• Core Size: 32bit
• Program Memory Size: 288KB
• Cpu Speed: 1GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 529
• Supply Voltage Range: 1.25V To 1.35V
• Operating Temperature Range: -20°C To +85°C
• Msl: MSL 3 - 168 Hours
• Embedded Interface Type: I2C, SPI, UART
• Lead Free Status / Rohs Status: Supplier Unconfirmed

4.3.5
The LVDS interface complies with TIA/EIA 644-A standard. See TIA/EIA STANDARD 644-A,
“Electrical Characteristics of Low Voltage Differential Signaling (LVDS) Interface Circuits” for details.
Table 17
4.4
This section defines the I/O Impedance parameters of the i.MX53xD processor for the following I/O
types:
Freescale Semiconductor
1
2
3
4
Output Differential Voltage
Output High Voltage
Output Low Voltage
Offset Voltage
Overshoot and undershoot conditions (transitions above OVDD and below GND) on switching pads must be held below 0.6 V,
and the duration of the overshoot/undershoot must not exceed 10% of the system clock cycle. Overshoot/undershoot must
be controlled through printed circuit board layout, transmission line impedance matching, signal line termination, or other
methods. Non-compliance to this specification may affect device reliability or cause permanent damage to the device.
DC level to the target DC level, VIL or VIH. Monotonic input transition time is from 0.1 ns to 1 s. VIL and VIH do not apply
when hysteresis is enabled.
Hysteresis of 250 mV is guaranteed over all operating conditions when hysteresis is enabled.
Use an off-chip pull resistor of less than 60 kΩ to override this keeper.
To maintain a valid level, the transitioning edge of the input must sustain a constant slew rate (monotonic) from the current
•
•
•
•
DC Electrical Characteristics
General Purpose I/O (GPIO)
Double Data Rate 3 I/O (DDR3) for DDR2/LVDDR2, LPDDR2, and DDR3 modes
Ultra High Voltage I/O (UHVIO)
LVDS I/O
shows the Low Voltage Differential Signaling (LVDS) DC electrical characteristics.
Output Buffer Impedance Characteristics
LVDS I/O DC Parameters
Output driver impedance is measured with “long” transmission line of
impedance Ztl attached to I/O pad and incident wave launched into
transmission lime. Rpu/Rpd and Ztl form a voltage divider that defines
specific voltage of incident wave relative to OVDD. Output driver
impedance is calculated from this voltage divider (see
i.MX53xD Applications Processors for Consumer Products, Rev. 3
Table 17. LVDS DC Electrical Characteristics
Symbol
V
V
V
V
OD
OH
OL
OS
Test Conditions
Rload=100Ω
padP, –padN
NOTE
1.125
1.25
Min
250
0.9
Figure
4).
1.375
1.025
Typ
350
1.2
Electrical Characteristics
1.375
Max
1.25
450
1.6
Unit
mV
V
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