MCIMX535DVV1C Freescale Semiconductor, MCIMX535DVV1C Datasheet - Page 28

• Manufacturer Part Number: MCIMX535DVV1C
• Description: IMX53 REV 2.1 COMM
• Manufacturer: Freescale Semiconductor

Specifications of MCIMX535DVV1C

• Rohs Compliant: YES
• Core Size: 32bit
• Program Memory Size: 288KB
• Cpu Speed: 1GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 529
• Supply Voltage Range: 1.25V To 1.35V
• Operating Temperature Range: -20°C To +85°C
• Msl: MSL 3 - 168 Hours
• Embedded Interface Type: I2C, SPI, UART
• Lead Free Status / Rohs Status: Supplier Unconfirmed

Electrical Characteristics
4.2.2
Power-down sequence should follow one of the following two options:
Option 1: Switch all supplies down simultaneously with further free discharge. A deviation of few
microseconds of actual power-down of the different power rails is acceptable.
Option 2: Switch down supplies, in any order, keeping the following rules:
4.2.3
4.3
This section includes the DC parameters of the following I/O types:
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Then the following rule should be kept: VDD_REG output impedance must be higher than 1 kΩ,
when inactive.
NVCC_CKIH must be powered down at the same time or after the UHVIO IO cell supplies (for
full supply list, refer to
microseconds of actual power-down of the different power rails is acceptable.
VDD_REG must be powered down at the same time or after NVCC_EMI_DRAM supply. A
deviation of few microseconds of actual power-down of the different power rails is acceptable.
If all of the following conditions are met:
— 1. VDD_REG is powered down to 0V (Not Hi-Z)
— 2. VDD_DIG_PLL and VDD_ANA_PLL are provided externally,
— 3. VDD_REG is powered down before VDD_DIG_PLL and VDD_ANA_PLL
All IO pins should not be externally driven while the IO power supply for the pin (NVCC_xxx) is
off. This can cause internal latch-up and malfunctions due to reverse current flows. For information
about IO power supply of each pin refer to “Power Rail” columns in pin list tables of
“Package Information and Contact Assignments.”
If not using SATA interface and the embedded thermal sensor, the VP and VPH should be
grounded. In particular, keeping VPH turned OFF while the VP is powered ON is not
recommended and might lead to excessive power consumption.
When internal clock source is used for SATA temperature monitor the USB_PHY supplies and
PLL need to be active because they are providing the clock.
If not using TVE the module, the TVDAC_DHVDD and TVDAC_AHVDDRGB can remain
floating. If only the GPIO pads in TVDAC_AHVDDRGB domain are in use, the supplies can be
set to GPIO pad voltage range (1.65 V to 3.1 V).
General Purpose I/O (GPIO)
Double Data Rate 3 I/O (DDR3) for DDR2/LVDDR2, LPDDR2 and DDR3 modes
Low Voltage I/O (LVIO)
Ultra High Voltage I/O (UHVIO)
LVDS I/O
I/O DC Parameters
Power-Down Sequence
Power Supplies Usage
i.MX53xD Applications Processors for Consumer Products, Rev. 3
Table 7
,
Ultra High voltage I/O (UHVIO) supplies
)
. A deviation of few
Freescale Semiconductor
Section 6,