MCIMX535DVV1C Freescale Semiconductor, MCIMX535DVV1C Datasheet - Page 179

• Manufacturer Part Number: MCIMX535DVV1C
• Description: IMX53 REV 2.1 COMM
• Manufacturer: Freescale Semiconductor

Specifications of MCIMX535DVV1C

• Rohs Compliant: YES
• Core Size: 32bit
• Program Memory Size: 288KB
• Cpu Speed: 1GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 529
• Supply Voltage Range: 1.25V To 1.35V
• Operating Temperature Range: -20°C To +85°C
• Msl: MSL 3 - 168 Hours
• Embedded Interface Type: I2C, SPI, UART
• Lead Free Status / Rohs Status: Supplier Unconfirmed

To support eMMC per the JESD209 option, top ball signals per
ALT2 is invoked for these I/O.
i.MX53 PoP supports 16- and 32-bit LPDDR2-800 per JESD209 with no additional PCB digital signal
connections. No signal cross reference is needed. The designer must ensure that the PCB routes power to
POP_VDD1, POP_VDD2, POP_VDDQ, POP_VDDCA, POP_VACC, and POP_VCCQMM,
POP_VCCMM, and POP_VDDMM. Appropriate discrete components must be employed for POP_ZQ,
DRAM_CALIBRATION, DDR_VREF, and POP_VCCQMM1.
6.3.2.3
Table 118
includes out of reset pad state.
Freescale Semiconductor
BOOT_MODE0
BOOT_MODE1
CKIH1
CKIH2
CKIL
CSI0_DAT10
CSI0_DAT11
CSI0_DAT12
CSI0_DAT13
CSI0_DAT14
CSI0_DAT15
Contact Name
Table 117. Additional Top Ball Connections for PoP eMMC
displays an alpha-sorted list of the signal assignments including power rails. The table also
RST
CLK
CMD
PoP 12 x 12 mm, Signal Assignments, Power Rails, and I/O
AA28
AB29
AC29
AC28
G13
R2
R7
U1
R1
T1
P1
eMMC Signal on
Port eSDHC3
Table 118. PoP 12 x 12 mm Signal Assignments, Power Rails, and I/O
i.MX53xD Applications Processors for Consumer Products, Rev. 3
—
—
—
—
—
—
—
—
—
—
—
NVCC_RESET
NVCC_RESET
NVCC_CKIH
NVCC_CKIH
NVCC_SRTC_POW ANALOG
NVCC_CSI
NVCC_CSI
NVCC_CSI
NVCC_CSI
NVCC_CSI
NVCC_CSI
Power Rail
PATA_DA0
PATA_IORDY
PATA_RESETB
Associated Top Ball
LVIO
LVIO
ANALOG
ANALOG
UHVIO
UHVIO
UHVIO
UHVIO
UHVIO
UHVIO
I/O Buffer
Type
ALT0
ALT0
ALT0
ALT0
—
ALT1
ALT1
ALT1
ALT1
ALT1
ALT1
Mode
Alt.
Package Information and Contact Assignments
Table 117
camp1_CKIH
camp2_CKIH
gpio5_GPIO[28]
gpio5_GPIO[29]
gpio5_GPIO[30]
gpio5_GPIO[31]
gpio6_GPIO[0]
gpio6_GPIO[1]
src_BOOT_MODE[0
]
src_BOOT_MODE[1
]
CKIL
Out of Reset Condition
Function
are provided. IOMUX mode
Input
Input
Input
Input
—
Input
Input
Input
Input
Input
Input
Direct
ion
1
100 KΩ PD
100 KΩ PD
Analog
Analog
—
100 KΩ PU
100 KΩ PU
360 KΩ PD
360 KΩ PD
360 KΩ PD
360 KΩ PD
Config./
Value
179