EP1S20F484C6N Altera, EP1S20F484C6N Datasheet - Page 290
![IC STRATIX FPGA 20K LE 484-FBGA](/photos/6/72/67258/544-484-fbga_sml.jpg)
EP1S20F484C6N
Manufacturer Part Number
EP1S20F484C6N
Description
IC STRATIX FPGA 20K LE 484-FBGA
Manufacturer
Altera
Series
Stratix®r
Datasheet
1.EP1S10F484I6N.pdf
(864 pages)
Specifications of EP1S20F484C6N
Number Of Logic Elements/cells
18460
Number Of Labs/clbs
1846
Total Ram Bits
1669248
Number Of I /o
361
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
484-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP1S20F484C6N
Manufacturer:
ALTERA
Quantity:
534
- Current page: 290 of 864
- Download datasheet (11Mb)
EP1S60 Devices
EP1S80 Devices
H
HSTL
Index–4
Column Pin
M-RAM
Row Pin
Column Pin
Global
Row Pin
Class I Specifications 4–14,
Class II Specifications 4–14,
Fast Regional Clock External I/O Timing
Global
Regional Clock External I/O Timing
Fast Regional Clock External I/O Timing
Global
Regional Clock External I/O Timing
Interface Locations
Fast Regional Clock External I/O Timing
Global
Regional Clock External I/O Timing
Fast Regional Clock External I/O Timing
Global
Regional Clock External I/O Timing
Fast Regional Clock External I/O Timing
Regional Clock External I/O Timing
Parameters
Parameters
Parameters
Parameters
Parameters
Parameters
Parameters
Parameters
Parameters
Parameters
Parameters
Parameters
Parameters
Parameters
Parameters
Clock
Clock
Clock
Clock
Clock
External
4–56
External
External
External
External
4–49
4–50
4–50
4–51
4–52
4–51
4–52
4–53
4–53
4–54
4–55
4–54
4–55
4–56
2–38
4–15
4–15
I/O
I/O
I/O
I/O
I/O
Timing
Timing
Timing
Timing
Timing
I
I/O
Standards
1.5-V 4–14,
1.8-V
2.5-V
3.3-V
Advanced I/O Standard Support
Column I/O Block Connection to the
Column Pin
Control Signal Selection per IOE
CTT I/O Specifications
Differential
External I/O Delay Parameters
GTL+ I/O Specifications
High-Speed
HyperTransport
I/O Banks
I/O Structure
I/O Support by Bank
IOE Structure
LVCMOS Specifications
LVDS
LVPECL Specifications
LVTTL Specifications
MultiVolt I/O Interface
MultiVolt I/O Support
Output Delay Adders for Fast Slew Rate
Output Delay Adders for Fast Slew Rate
Output Delay Adders for Slow Slew Rate
Package Options & I/O Pin Counts
Receiver Input Waveforms for Differential
Interconnect
Termination
Support
Specifications
Input
on Column Pins
on Row Pins
on Column Pins
4–13
I/O Specifications
I/O Specifications
I/O Specifications
LVDS I/O Specifications
PCI Specifications
PCML Specifications
Input Delay Adders
Stratix Device Handbook, Volume 1
Performance
2–125
4–15
2–103
LVDS
2–104
2–105
2–130
Differential
2–107
2–128
4–69
4–9
2–126
4–3
Altera Corporation
Input
4–68
4–70
on
4–8
2–130
4–16
2–129
4–3
4–10
4–9
4–4
4–4
4–3
4–66
Technology
4–8
Fast
4–66
On-Chip
4–6
2–109
2–122
1–4
PLL
I/O
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