EP1S20F484C6N Altera, EP1S20F484C6N Datasheet - Page 517
![IC STRATIX FPGA 20K LE 484-FBGA](/photos/6/72/67258/544-484-fbga_sml.jpg)
EP1S20F484C6N
Manufacturer Part Number
EP1S20F484C6N
Description
IC STRATIX FPGA 20K LE 484-FBGA
Manufacturer
Altera
Series
Stratix®r
Datasheet
1.EP1S10F484I6N.pdf
(864 pages)
Specifications of EP1S20F484C6N
Number Of Logic Elements/cells
18460
Number Of Labs/clbs
1846
Total Ram Bits
1669248
Number Of I /o
361
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
484-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP1S20F484C6N
Manufacturer:
ALTERA
Quantity:
534
- Current page: 517 of 864
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Figure 5–31.
High-Speed
Interface Pin
Locations
Altera Corporation
July 2005
×
2 Data Rate Transmitter Channel with Serialization Factor of 8
Stratix
Logic
Array
PLL
D0, D2,
D1, D3,
×1
D4, D6
D5, D7
×4
×1
Figure 5–30.
Stratix high-speed interface pins are located at the edge of the package to
limit the possible mismatch between a pair of high-speed signals. Stratix
devices have eight programmable I/O banks.
pins and their location relative to the package.
datain_h
outclock
datain_l
dataout
Register
Register
XX
XX
Shift
Shift
×
2 Timing Relation between Parallel Data & Clock
XX
B0
A0
High-Speed Differential I/O Interfaces in Stratix Devices
A0
DDR IOE
B0
DFF
DFF
B1
A1
A1
Stratix Device Handbook, Volume 2
B1
Figure 5–32
B2
A2
A2
dataout
inclock
B2
shows the I/O
B3
A3
A3
5–45
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