EP1S20F484C6N Altera, EP1S20F484C6N Datasheet - Page 395

• Manufacturer Part Number: EP1S20F484C6N
• Description: IC STRATIX FPGA 20K LE 484-FBGA
• Manufacturer: Altera
• Series: Stratix®r

Specifications of EP1S20F484C6N

• Number Of Logic Elements/cells: 18460
• Number Of Labs/clbs: 1846
• Total Ram Bits: 1669248
• Number Of I /o: 361
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Conclusion
Altera Corporation
July 2005
Figure 2–16. Mixed-Port Read-During-Write: OLD_DATA
For mixed-port read-during-write operation of the same address location
of a M-RAM block, the RAM outputs are unknown, as shown in
Figure
Figure 2–17. Mixed-Port Read-During-Write: DONT_CARE
Mixed-port read-during-write is not supported when two different clocks
are used in a dual-port RAM. The output value will be unknown during
a mixed-port read-during-write operation.
TriMatrix memory, an enhanced RAM architecture with extremely high
memory bandwidth in Stratix and Stratix GX devices, gives advanced
control of memory applications with features such as byte enables, parity
bit storage, and shift-register mode, as well as mixed-port width support
and true dual-port mode.
2–17.
TriMatrix Embedded Memory Blocks in Stratix & Stratix GX Devices
address A and
address A and
address B
address B
data_out
data_out
data_in
data_in
inclock
inclock
Port A
Port A
Port B
Port B
Port A
Port A
Port B
Port B
wren
wren
wren
wren
A
A
Unknown
Old
Address Q
Address Q
Stratix Device Handbook, Volume 2
A
B
B
B
B
2–27