EP1S20F484C6N Altera, EP1S20F484C6N Datasheet - Page 418
![IC STRATIX FPGA 20K LE 484-FBGA](/photos/6/72/67258/544-484-fbga_sml.jpg)
EP1S20F484C6N
Manufacturer Part Number
EP1S20F484C6N
Description
IC STRATIX FPGA 20K LE 484-FBGA
Manufacturer
Altera
Series
Stratix®r
Datasheet
1.EP1S10F484I6N.pdf
(864 pages)
Specifications of EP1S20F484C6N
Number Of Logic Elements/cells
18460
Number Of Labs/clbs
1846
Total Ram Bits
1669248
Number Of I /o
361
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
484-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP1S20F484C6N
Manufacturer:
ALTERA
Quantity:
534
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DDR Memory Support Overview
Figure 3–11. Extending the OE Disable by Half-a-Clock Cycle for a Write Transaction
Note to
(1)
3–22
Stratix Device Handbook, Volume 2
from System Clock)
−90° phase shifted
The waveform reflects the software simulation result. The OE signal is an active low on the device. However, the
Quartus II software implements this signal as an active high and automatically adds an inverter before the A
register D input.
(outclock for DQS)
(from logic array)
(from logic array)
(from logic array)
(from logic array)
(outclock for DQ,
Figure
System clock
OE for DQS
Write Clock
OE for DQ
datain_h
datain_l
DQS
3–11:
DQ
90˚
Figures 3–12
DQS signals.
and
by Half
a Clock
Delay
Cycle
3–13
summarize the IOE registers used for the DQ and
Preamble
D0
D1
D0
D1
D2
D2
D3
Note (1)
Altera Corporation
D3
Postamble
June 2006
OE
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