EP1S20F484C6N Altera, EP1S20F484C6N Datasheet - Page 375

• Manufacturer Part Number: EP1S20F484C6N
• Description: IC STRATIX FPGA 20K LE 484-FBGA
• Manufacturer: Altera
• Series: Stratix®r

Specifications of EP1S20F484C6N

• Number Of Logic Elements/cells: 18460
• Number Of Labs/clbs: 1846
• Total Ram Bits: 1669248
• Number Of I /o: 361
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Using TriMatrix
Memory
Altera Corporation
July 2005
f
The TriMatrix memory blocks include input registers that synchronize
writes and output registers to pipeline designs and improve system
performance. All TriMatrix memory blocks are pipelined, meaning that
all inputs are registered, but outputs are either registered or
combinatorial. TriMatrix memory can emulate a flow-through memory
by using combinatorial outputs.
For more information, see AN 210: Converting Memory from Asynchronous
to Synchronous for Stratix & Stratix GX Designs.
Depending on the TriMatrix memory block type, the memory can have
various modes, including:
■
■
■
■
■
■
Implementing Single-Port Mode
Single-port mode supports non-simultaneous reads and writes.
Figure 2–2
memory. All memory block types support the single-port mode.
Figure 2–2. Single-Port Memory
Note to
(1)
M4K memory blocks can also be divided in half and used for two
independent single-port RAM blocks. The Altera Quartus II software
automatically uses this single-port memory packing when running low
on memory resources. To force two single-port memories into one M4K
block, first ensure that each of the two independent RAM blocks is equal
to or less than half the size of the M4K block. Second, assign both single-
port RAMs to the same M4K block.
Single-port
Simple dual-port
True dual-port (bidirectional dual-port)
Shift-register
ROM
FIFO
Two single-port memory blocks can be implemented in a single M4K block.
Figure
TriMatrix Embedded Memory Blocks in Stratix & Stratix GX Devices
shows the single-port memory configuration for TriMatrix
2–2:
data[ ]
address[ ]
wren
inclocken
inaclr
inclock
Note (1)
Stratix Device Handbook, Volume 2
outclocken
outclock
outaclr
q[ ]
2–7