EP1S20F484C6N Altera, EP1S20F484C6N Datasheet - Page 754

• Manufacturer Part Number: EP1S20F484C6N
• Description: IC STRATIX FPGA 20K LE 484-FBGA
• Manufacturer: Altera
• Series: Stratix®r

Specifications of EP1S20F484C6N

• Number Of Logic Elements/cells: 18460
• Number Of Labs/clbs: 1846
• Total Ram Bits: 1669248
• Number Of I /o: 361
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Configuration Schemes
11–36
Stratix Device Handbook, Volume 2
Notes to
(1)
(2)
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
CF2WS
DSU
DH
CSSU
CSH
WSP
CFG
WS2B
BUSY
RDY2WS
WS2RS
RS2WS
RSD7
CD2UM
STATUS
CF2CD
CF2ST0
CF2ST1
Table 11–10. PPA Timing Parameters for Stratix & Stratix GX Devices
Symbol
The minimum and maximum numbers apply only if the internal oscillator is chosen as the clock source for starting
up the device. If the clock source is CLKUSR, multiply the clock period by 136 to obtain this value.
This value is obtained if you do not delay configuration by extending the nstatus to low pulse width.
Table
11–10:
nCONFIG
Data setup time before rising edge on
Data hold time after rising edge on
Chip select setup time before rising edge on
Chip select hold time after rising edge on
nWS
nCONFIG
nWS
RDYnBSY
RDYnBSY
nWS
nRS
nRS
CONF_DONE
nSTATUS
nCONFIG
nCONFIG
nCONFIG
f
low pulse width
rising edge to
rising edge to
rising edge to
falling edge to
high to first rising edge on
low pulse width
low pulse width
rising edge to
low pulse width
low to
low to
high to
Table 11–10
configuration
For information on how to create configuration and programming files
for this configuration scheme, see the Software Settings section in the
Configuration Handbook, Volume 2.
JTAG Programming & Configuration
The JTAG has developed a specification for boundary-scan testing. This
boundary-scan test (BST) architecture offers the capability to efficiently
test components on printed circuit boards (PCBs) with tight lead spacing.
The BST architecture can test pin connections without using physical test
high to user mode
CONF_DONE
nSTATUS
nSTATUS
RDYnBSY
nRS
nWS
DATA7
falling edge
rising edge
Parameter
nWS
defines the Stratix and Stratix GX timing parameters for PPA
valid with
low
high
low
rising edge
low
(1)
nWS
nWS
RDYnBSY
nWS
nWS
nWS
signal
Min
40
10
10
15
40
15
15
15
10
0
0
7
6
Altera Corporation
40
40
Max
800
800
20
45
20
20
(2)
(2)
July 2005
Units
µs
ns
ns
ns
ns
ns
µs
ns
ns
ns
ns
ns
ns
µs
µs
ns
ns
µs