EP1S20F484C6N Altera, EP1S20F484C6N Datasheet - Page 326

• Manufacturer Part Number: EP1S20F484C6N
• Description: IC STRATIX FPGA 20K LE 484-FBGA
• Manufacturer: Altera
• Series: Stratix®r

Specifications of EP1S20F484C6N

• Number Of Logic Elements/cells: 18460
• Number Of Labs/clbs: 1846
• Total Ram Bits: 1669248
• Number Of I /o: 361
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Enhanced PLLs
1–16
Stratix Device Handbook, Volume 2
Programmable Duty Cycle
The programmable duty cycle allows enhanced PLLs to generate clock
outputs with a variable duty cycle. This feature is supported on each
enhanced PLL post-scale counter (g0..g3, l0..l3, e0..e3). The duty cycle
setting is achieved by a low and high time count setting for the post-scale
counters. The Quartus II software uses the frequency input and the
required multiply or divide rate to determine the duty cycle choices. The
precision of the duty cycle is determined by the post-scale counter value
chosen on an output. The precision is defined by 50% divided by the post-
scale counter value. The closest value to 100% is not achievable for a given
counter value. For example, if the g0 counter is 10, then steps of 5% are
possible for duty cycle choices between 5 to 90%.
If the device uses external feedback, you must set the duty cycle for the
counter driving off the device to 50%.
General Advanced Clear & Enable Control
There are several control signals for clearing and enabling PLLs and PLL
outputs. You can use these signals to control PLL resynchronization and
gate PLL output clocks for low-power applications.
The pllenable pin is a dedicated pin that enables/disables PLLs. When
the pllenable pin is low, the clock output ports are driven by GND and
all the PLLs go out of lock. When the pllenable pin goes high again, the
PLLs relock and resynchronize to the input clocks. You can choose which
PLLs are controlled by the pllenable signal by connecting the
pllenable input port of the altpll megafunction to the common
pllenable input pin.
The areset signals are reset/resynchronization inputs for each PLL. The
areset signal should be asserted every time the PLL loses lock to
guarantee correct phase relationship between the PLL output clocks.
Users should include the areset signal in designs if any of the following
conditions are true:
■
■
The device input pins or logic elements (LEs) can drive these input
signals. When driven high, the PLL counters reset, clearing the PLL
output and placing the PLL out of lock. The VCO sets back to its nominal
setting (~700 MHz). When driven low again, the PLL resynchronizes to
its input as it relocks. If the target VCO frequency is below this nominal
PLL reconfiguration or clock switchover enables in the design
Phase relationships between output clocks need to be maintained
after a loss of lock condition
Altera Corporation
July 2005