EP1S20F484C6N Altera, EP1S20F484C6N Datasheet - Page 807

IC STRATIX FPGA 20K LE 484-FBGA

EP1S20F484C6N

Manufacturer Part Number
EP1S20F484C6N
Description
IC STRATIX FPGA 20K LE 484-FBGA
Manufacturer
Altera
Series
Stratix®r
Datasheet

Specifications of EP1S20F484C6N

Number Of Logic Elements/cells
18460
Number Of Labs/clbs
1846
Total Ram Bits
1669248
Number Of I /o
361
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
484-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-

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0
Figure 12–16. Converting POF Programming File to Intel HEX Format
Altera Corporation
September 2004
The initial programming file (POF) can be converted to an Intel
Hexadecimal format file (*.HEXOUT) using the Quartus II CPF utility.
See
Partial Programming File Generation
The enhanced Quartus II CPF utility allows an existing application
configuration page to be replaced with new data. Partial programming
files are generated to perform such configuration data updates.
In order to generate a partial programming file, you have to input the
initial programming file (POF) and new configuration data (SOF) to the
Quartus II CPF utility. In addition, you have to specify the addressing
mode (auto or manual) that was used during initial POF creation. And if
Figure
12–16.
Remote System Configuration with Stratix & Stratix GX Devices
Stratix Device Handbook, Volume 2
12–29

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