EP1S20F484C6N Altera, EP1S20F484C6N Datasheet - Page 664
![IC STRATIX FPGA 20K LE 484-FBGA](/photos/6/72/67258/544-484-fbga_sml.jpg)
EP1S20F484C6N
Manufacturer Part Number
EP1S20F484C6N
Description
IC STRATIX FPGA 20K LE 484-FBGA
Manufacturer
Altera
Series
Stratix®r
Datasheet
1.EP1S10F484I6N.pdf
(864 pages)
Specifications of EP1S20F484C6N
Number Of Logic Elements/cells
18460
Number Of Labs/clbs
1846
Total Ram Bits
1669248
Number Of I /o
361
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
484-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP1S20F484C6N
Manufacturer:
ALTERA
Quantity:
534
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Interfaces
8–20
Stratix Device Handbook, Volume 2
Figure 8–15. XAUI Location
Functional Description
XAUI can replace the 32 bits of parallel data required by XGMII for
transmission with just 4 lanes of serial data. XAUI uses clock data
recovery (CDR) to eliminate the need for separate clock signals. 8b/10b
encoding is employed on the data stream to embed the clock in the data.
The 8b/10b protocol to encode an 8-bit word stream to 10-bit codes that
results in a DC-balanced serial stream and eases the receiver
synchronization. To support 10-Gigabit Ethernet, each lane must run at a
speed of at least 2.5 Gbps. Using 8b/10b encoding increases the rate for
each lane to 3.125 Gbps, which will be supported in Stratix GX Gbps
devices. This circuitry is supported by the embedded 3.125 Gbps
transceivers within the Stratix GX architecture. You can find more
XGMII Extender
Sublayer (XGXS)
Reconciliation
XGXS
MAC
PHY
XGMII
XAUI
XGMII
Altera Corporation
July 2005
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