EP1S20F484C6N Altera, EP1S20F484C6N Datasheet - Page 750

• Manufacturer Part Number: EP1S20F484C6N
• Description: IC STRATIX FPGA 20K LE 484-FBGA
• Manufacturer: Altera
• Series: Stratix®r

Specifications of EP1S20F484C6N

• Number Of Logic Elements/cells: 18460
• Number Of Labs/clbs: 1846
• Total Ram Bits: 1669248
• Number Of I /o: 361
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Configuration Schemes
11–32
Stratix Device Handbook, Volume 2
be monitored, reading the state of the configuration data by strobing nRS
low saves a system I/O port. Do not drive data onto the data bus while
nRS is low because it causes contention on DATA7. If the nRS pin is not
used to monitor configuration, you should tie it high. To simplify
configuration, the microprocessor can wait for the total time of
t
After configuration, the nCS, CS, nRS, nWS, and RDYnBSY pins act as user
I/O pins. However, if the PPA scheme is chosen in the Quartus II
software, these I/O pins are tri-stated by default in user mode and should
be driven by the microprocessor. To change the default settings in the
Quartus II software, select Device & Pin Option (Compiler Setting
menu).
If the Stratix or Stratix GX device detects an error during configuration, it
drives nSTATUS low to alert the microprocessor. The microprocessor can
then pulse nCONFIG low to restart the configuration process.
Alternatively, if the Auto-Restart Configuration on Frame Error option
is turned on, the Stratix or Stratix GX device releases nSTATUS after a
reset time-out period. After nSTATUS is released, the microprocessor can
reconfigure the Stratix or Stratix GX device. At this point, the
microprocessor does not need to pulse nCONFIG low.
The microprocessor can also monitor the CONF_DONE and INIT_DONE
pins to ensure successful configuration. The microprocessor must
monitor the nSTATUS pin to detect errors and the CONF_DONE pin to
determine when programming completes (CONF_DONE goes high one
byte early in parallel mode). If the microprocessor sends all configuration
data and starts initialization but CONF_DONE is not asserted, the
microprocessor must reconfigure the Stratix or Stratix GX device.
By default, the INIT_DONE is disabled. You can enable the INIT_DONE
output by turning on the Enable INIT_DONE output option in the
Quartus II software. If you do not turn on the Enable INIT_DONE
output option in the Quartus II software, you are advised to wait for the
maximum value of t
goes high to ensure the device has been initialized properly and that it has
entered user mode.
During configuration and initialization, and before the device enters user
mode, the microprocessor must not drive the CONF_DONE signal low.
1
BUSY
(max) + t
If the optional CLKUSR pin is used and nCONFIG is pulled low
to restart configuration during device initialization, you need to
ensure that CLKUSR continues toggling during the time
nSTATUS is low (maximum of 40 s).
RDY2WS
CD2UM
+ t
W2SB
(see
before sending the next data bit.
Table
11–10) after the CONF_DONE signal
Altera Corporation
July 2005